MAX192BEWP+ Maxim Integrated Products, MAX192BEWP+ Datasheet - Page 12

• Manufacturer Part Number: MAX192BEWP+
• Description: IC ADC 10BIT SERIAL 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS), ADCr

Specifications of MAX192BEWP+

• Resolution (bits): 10 b
• Sampling Rate (per Second): 133k
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 800 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulling CS high prevents data from being clocked into
the MAX192 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in
and out of the MAX192 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time,
t
The falling edge of CS does not start a conversion on
the MAX192. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on the falling edge of SCLK,
Low-Power, 8-Channel,
Serial 10-Bit ADC
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7. Detailed Serial-Interface Timing
12
AZ
SSTRB
DOUT
A/D STATE
SCLK
, is kept above 1.5µs.
DIN
CS
______________________________________________________________________________________
DOUT
SCLK
DIN
CS
START SEL2 SEL1 SEL0
1
t
CSH
IDLE
t
DV
RB1
t
CSS
4
RB1
t
UNI/
DS
BIP
t
1.5µs (CLK = 2MHz)
DH
SGL/
DIF
ACQUISITION
t
ACQ
PD1
PD0
Data Framing
8
t
CL
t
CH
MSB
B9
B8
B7
12
RB2
B6
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as:
If a falling edge on CS forces a start bit before bit 3
(B3) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX192 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CS is low and SCLK is contin-
uous, guarantee a start bit by first clocking in 16 zeros.
RB2
CONVERSION
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after V
The first high bit clocked into DIN after bit 3 of a
conversion in progress is clocked onto the DOUT pin.
B5
B4
B3
16
t
DO
B2
B1
LSB
B0
OR
t
CSH
S1
20
RB3
SO
RB3
FILLED WITH
ZEROS
t
IDLE
TR
DD
is applied.
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