MAX192BEWP+ Maxim Integrated Products, MAX192BEWP+ Datasheet - Page 16

• Manufacturer Part Number: MAX192BEWP+
• Description: IC ADC 10BIT SERIAL 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS), ADCr

Specifications of MAX192BEWP+

• Resolution (bits): 10 b
• Sampling Rate (per Second): 133k
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 800 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power, 8-Channel,
Serial 10-Bit ADC
Table 5. Worst-Case Power-Up Delay Times
Table 6. Software Shutdown and Clock
Mode
tors that will not discharge more than 1/2LSB while shut
down. In shutdown, the capacitor has to supply the cur-
rent into the reference (1.5µA typ) and the transient cur-
rents at power-up.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked
out while the MAX192 has already entered a software
power-down.
The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX192. Following the start bit,
the data input word or control byte also determines
clock and power-down modes. For example, if the DIN
word contains PD1 = 1, then the chip will remain pow-
ered up. If PD1 = 0, a power-down will resume after
one conversion.
16
Buffer
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Reference
PD1
1
1
0
0
______________________________________________________________________________________
PD0
1
0
1
0
Device Mode
External Clock Mode
Internal Clock Mode
Fast Power-Down Mode
Full Power-Down Mode
Reference-
Buffer
Compensation
Mode
Internal
Internal
External
External
Software Power-Down
VREF
Capacitor
(µF)
4.7
4.7
Power-
Down
Mode
Fast
Full
Fast
Full
Fast
Full
The SHDN pin places the converter into the full
power-down mode. Unlike with the software shutdown
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
The MAX192 auto power-down modes can save con-
siderable power when operating at less than maximum
sample rates. The following discussion illustrates the
various power-down sequences.
The following examples illustrate two different
power-down sequences. Other combinations of clock
rates, compensation modes, and power-down modes
may give lowest power consumption in other applica-
tions.
Figure 14a depicts the MAX192 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensa-
tion. A 0.01µF bypass capacitor at REFADJ forms an
Table 7. Hard-Wired Shutdown and
Compensation Mode
Floating
S S H H D D N N
State
1
0
Device
Mode
Enabled
Enabled
Full Power-Down N/A
Power-Up
Delay
(sec)
5µ
300µ
See Figure 14c
See Figure 14c
2µ
2µ
Power-Down Sequencing
Conversions/Channel/Second
Lowest Power at up to 500
Internal Compensation
External Compensation
Reference-Buffer
Compensation
Hardware Power-Down
133
133
133
133
26
26
Maximum
Sampling
Rate (ksps)