AD2S1200YSTZ Analog Devices Inc, AD2S1200YSTZ Datasheet - Page 11

• Manufacturer Part Number: AD2S1200YSTZ
• Description: IC CONV R/D 12-BIT W/OSC 44-LQFP
• Manufacturer: Analog Devices Inc
• Type: R/D Converterr

Specifications of AD2S1200YSTZ

• Resolution (bits): 12 b
• Data Interface: Serial, Parallel
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD2S1200CBZ - BOARD EVAL FOR AD2S1200
• Sampling Rate (per Second): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CONNECTING THE CONVERTER
Refer to Figure 5. Ground should be connected to the AGND
pin and DGND pin. Positive power supply V
should be connected to the AV
values for the decoupling capacitors are 10 nF and 4.7 µF,
respectively. These capacitors should be placed as close to the
device pins as possible, and should be connected to both AV
and DV
changed from the nominal value of 10 kHz using FS1 and FS2.
Typical values for the oscillator decoupling capacitors are 20 pF.
Typical values for the reference decoupling capacitors are 10 µF
and 0.01 µF, respectively.
5V
10nF
DD
10
11
1
2
3
4
5
6
7
8
9
. If desired, the reference oscillator frequency can be
DV
Figure 5. Connecting the AD2S1200 to a Resolver
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
DD
10µF
S2
AD2S1200
S6
4.7µF
DD
S3
4.7µF
pin and DV
5V
10nF
20pF
S1
5V
10nF
R2
R1
8.912
DGND
MHz
DD
DD
BUFFER
CIRCUIT
= +5 V dc ± 5%
pin. Typical
20pF
33
32
31
30
29
28
27
26
25
24
23
RESET
BUFFER
CIRCUIT
DD
Rev. 0 | Page 11 of 24
The gain of the buffer depends on the type of resolver used.
Since the specified excitation output amplitudes are matched to
the specified Sin/Cos input amplitudes, the gain of the buffer is
determined by the attenuation of the resolver.
In this recommended configuration, the converter introduces a
V
Of course, the SinLO and CosLO signals may be connected to a
different potential relative to ground, as long as the Sin and Cos
signals respect the recommended specifications. Note that since
the EXC/ EXC outputs are differential, there is an inherent gain
of 2×.
For example, if the primary to secondary turns ratio is 2:1, the
buffer will have unity gain. Likewise, if the turns ratio is 5:1, the
gain of the buffer should be 2.5×. Figure 6 suggests a buffer
circuit. The gain of the circuit is
V
need for a negative supply.
Separate screened twisted cable pairs are recommended for
analog inputs Sin/SinLO and Cos/CosLO. The screens should
terminate to REFOUT. To achieve the dynamic performance
specified, an 8.192 MHz crystal must be used.
REF
REF
EXC/EXC
/2 offset in the Sin, Cos signals coming from the resolver.
is set so that V
(V
5V
IN
and
)
V
442Ω
OUT
R1
(V
OUT
=
REF
1.24kΩ



is always a positive value, eliminating the
)
Figure 6. Buffer Circuit
Gain −
V
REF
12V
R2
=
×
 +


1
(
R
/ 2
R
R
2
1
R
12V



) 1



−



R
R
2.7kΩ
2.7kΩ
2
1
×
33Ω
33Ω
AD2S1200
V
12V
IN



V
OUT