TDA8754HL/21/C1,51 NXP Semiconductors, TDA8754HL/21/C1,51 Datasheet - Page 43

• Manufacturer Part Number: TDA8754HL/21/C1,51
• Description: IC TRPL 8BIT VIDEO ADC LQFP144
• Manufacturer: NXP Semiconductors
• Type: Video ADCr

Specifications of TDA8754HL/21/C1,51

• Package / Case: 144-LQFP
• Resolution (bits): 8 b
• Sampling Rate (per Second): 210M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935272704518; TDA8754HL21BE-T; TDA8754HL21BE-T

Philips Semiconductors
Table 75:
T
9397 750 14984
Product data sheet
Symbol
G
R, G and B clamp
N
Phase-Locked Loop (PLL); see
J
DR
f
f
Analog-to-Digital Converters (ADCs); minimum coarse gain
f
INL
DNL
ENOB
S/N
SFDR
THD
Data timing; 10 pF load; see
t
t
t
LV-TTL digital inputs and outputs
Input pins CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK and CLP
V
V
Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO, HSYNCO,
VSYNCO, FIELDO, CLPO, CKREFO and CSYNCO
V
V
Data clock output
Output pin CKDATA
f
Data outputs
Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO and CSYNCO
f
PLL
ref
s(max)
d(o)
h(o)
su(o)
CKDATA(max)
data(max)
amb
PLL(p-p)
step
ct
IL
IH
OL
OH
clamp
E(rms)
step
= 25 C unless otherwise specified.
Characteristics
Parameter
full-scale channel-to-channel
matching (RMS value)
clamp level accuracy
long term PLL phase jitter
(peak-to-peak value)
divider ratio
output clock frequency
reference clock frequency
number of phase shift steps
from drift
phase shift step
maximum sampling frequency
integral non-linearity
differential non-linearity
effective number of bits
crosstalk
signal-to-noise ratio
spurious free dynamic range
total harmonic distortion
output delay
output hold time
output setup time
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
maximum buffer frequency
maximum buffer frequency
…continued
Figure 4
Table 76
Conditions
minimum coarse gain;
code = 32
f
20
f
f
f
f
f
f
f
f
I
I
CLK
clk
clk
clk
clk
clk
clk
clk
clk
OH
OL
= 270 MHz; DR = 2160
= 270 MHz; f
= 270 MHz; f
= 270 MHz; f
= 270 MHz
= 270 MHz; f
= 270 MHz; f
= 270 MHz; f
Rev. 06 — 16 June 2005
= 1 mA
= 1 mA
= 25 MHz, clamp code =
i
i
i
i
i
i
= 10 MHz
= 10 MHz
= 10 MHz
= 10 MHz
= 10 MHz
= 10 MHz
Triple 8-bit video ADC up to 270 Msps
Min
-
-
-
100
10
15
-
-
270
-
-
-
-
-
48
-
-
1.9
-
0
2.0
-
2.4
-
-
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Typ
-
-
390
-
-
-
-
11.25
-
7.6
-
48
55
4
-
-
-
-
-
-
140
70
0.6
0.25
55
[1]
TDA8754
Max
2.5
1
480
4095
270
150
2
-
-
-
-
-
5.2
-
6
0.8
V
0.4
-
-
-
1.3
0.6
45
48
CCD(TTL)
Unit
%
bit
ps
MHz
kHz
deg
MHz
bits
bits
bits
dB
dB
dB
dB
ns
ns
ns
V
V
V
V
MHz
MHz
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