MCP4011-502E/SN Microchip Technology, MCP4011-502E/SN Datasheet - Page 43

• Manufacturer Part Number: MCP4011-502E/SN
• Description: IC DGTL POT 5K 1CH 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4011-502E/SN

• Package / Case: 8-SOIC (3.9mm Width)
• Taps: 64
• Resistance (ohms): 5K
• Number Of Circuits: 1
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Volatile
• Interface: Up/Down
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 5K
• Number Of Pots: Single
• Taps Per Pot: 64
• Resistance: 5 KOhms
• Wiper Memory: Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Supply Current: 0.045 mA (Typ)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.0
In the design of a system with the MCP401X devices,
the following considerations should be taken into
account:
• The Power Supply
• The Layout
7.1
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity.
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (V
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
FIGURE 7-1:
Connections.
© 2006 Microchip Technology Inc.
SS
should reside on the analog plane.
W
A
B
DESIGN CONSIDERATIONS
Power Supply Considerations
0.1 µF
V
V
DD
SS
Typical Microcontroller
Figure 7-1
0.1 µF
U/D
CS
V
V
illustrates an
DD
SS
DD
DD
) as
and
7.2
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4011/2/3/4’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
Layout Considerations
MCP4011/2/3/4
DS21978C-page 43