DS1859E-050+ Maxim Integrated Products, DS1859E-050+ Datasheet - Page 20

• Manufacturer Part Number: DS1859E-050+
• Description: IC RES TEMP 50/50K 3MON 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1859E-050+

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.85 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 50K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 50 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 2.85 V to 5.5 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.85 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
20
Table 01h (continued)
LOCATION
MEMORY
8A to 8B
(hex)
8C
8D
8E
8F
____________________________________________________________________
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
EEPROM/
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
SRAM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DEFAULT
SETTING
(hex)
A2
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Device address
LOCATION
NAME OF
Reserved
Reserved
MON1
MON1
MON1
MON2
MON2
MON2
MON3
MON3
MON3
ADFIX
ADEN
MPEN
APEN
INV1
INV2
—
—
—
—
—
—
—
2
1
0
2
1
0
2
1
0
Controls if the device responds to one or two device
addresses (see the Memory Description section and
Table 5).
Controls the means by which Main and Auxiliary Device
addresses are set (see the Memory Description section
and Table 5).
Controls auxiliary write protect. See the Memory
Description section.
Controls main write protect. See the Memory Description
section.
Configures buffer 1 with OUT1 = MINT +
(INV1 [XOR] IN1).
Configures buffer 2 with OUT2 = INV2 [XOR] IN2.
Contains Main Device address if the bit ADFIX = 1. If
ADFIX = 0, then address A2h is used.
Contains bits used to perform right shift operations on the
A/D output converter. See the Right Shift A/D Conversion
Result section.
Right Shift Control MSB
Right Shift Control LSB
Right Shift Control MSB
Right Shift Control LSB
Contains bits used to perform right shift operations on the
A/D output converter. See the Right Shift A/D Conversion
Result section.
Right Shift Control MSB
Right Shift Control LSB
FUNCTION
—