DS1807E+ Maxim Integrated Products, DS1807E+ Datasheet - Page 6

• Manufacturer Part Number: DS1807E+
• Description: IC POT ADDRESS 2X AUDIO 14-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1807E+

• Taps: 64 + Mute
• Resistance (ohms): 45K
• Number Of Circuits: 2
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 45K
• Number Of Pots: Dual
• Taps Per Pot: 64
• Resistance: 45 KOhms
• Wiper Memory: Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 40 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Tolerance: 20 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1807 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
SLAVE ADDRESS
A control byte is the first byte received following the START condition from the master device. The
control byte consists of a 4-bit control code. For the DS1807, this is set as 0101 binary for read/write
operations. The next 3 bits of the control byte are the device select bits (A2, A1, and A0). They are used
by the master device to select which of eight devices are to be accessed. The select bits are in effect the
three least significant bits of the slave address. The last bit of the control byte (R/W) defines the operation
to be performed. When set to a 1 a read operation is selected, and when set to a 0 a write operation is
selected. Figure 5 shows the control byte structure for the DS1807.
Following the START condition, the DS1807 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the 0101 address code and appropriate device select bits, the slave
device outputs an acknowledge signal on the SDA line.
COMMAND AND PROTOCOL
The command and protocol structure of the DS1807 allows the user to read or write the potentiometer(s).
The command structures for the part are presented in Figures 6 and 7. Potentiometer data values and
control and command values are always transmitted most significant bit (MSB) first. During
communications, the receiving unit always generates the acknowledgement.
READING THE DS1807
As shown in Figure 6, the DS1807 provides one read command operation. This operation allows the user
to read both potentiometers. Specifically, the R/W bit of the control byte is set equal to a 1 for a read
operation. Communication to read the DS1807 begins with a START condition which is issued by the
master device. The control byte from the master device will follow the START condition. Once the
control byte has been received by the DS1807, the part will respond with an ACKNOWLEDGE. The
read/write bit of the control byte as stated should be set equal to 1 for reading the DS1807.
master is the control byte (or slave address). Next follows a number of data bytes. The slave returns
an acknowledge bit after each received. byte.
transmitted by the master. The slave then returns an acknowledge bit . Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1807 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
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