AD5172BRMZ50 Analog Devices Inc, AD5172BRMZ50 Datasheet - Page 21

• Manufacturer Part Number: AD5172BRMZ50
• Description: IC DGTL POT DUAL 50K 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5172BRMZ50

• Memory Type: Non-Volatile
• Temperature Coefficient: 35 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K
• End To End Resistance: 50kohm
• Resistance Tolerance: ± 20%
• No. Of Steps: 256
• Control Interface: Serial, I2C, 2-Wire
• No. Of Pots: Dual
• Supply Voltage Range: 2.7V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
This section describes how the 2-wire, I
protocol operates.
The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 48 and Figure 49).
The following byte is the slave address byte, which consists of
the slave address followed by an R/ W bit (this bit determines
whether data is read from or written to the slave device). The
AD5172 has a fixed slave address byte, whereas the AD5173
has two configurable address bits, AD0 and AD1 (see
and
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its serial register. If the
R/ W bit is high, the master reads from the slave device. If the
R/ W bit is low, the master writes to the slave device.
In write mode, the second byte is the instruction byte. The first
bit (MSB) of the instruction byte is the RDAC subaddress select
bit. Logic low selects Channel 1; logic high selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A while shorting the wiper to Terminal B.
This operation yields almost 0 Ω in rheostat mode or 0 V in
potentiometer mode. It is important to note that the shutdown
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to the
RDAC. In addition, during shutdown, new settings can be
programmed. When the part is returned from shutdown, the
corresponding VR setting is applied to the RDAC.
The third MSB, T, is the OTP programming bit. A logic high
blows the polyfuses and programs the resistor setting permanently.
The OTP program time is 400 ms.
The fourth MSB must always be at Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a logic high,
OW allows the RDAC setting to be changed even after the internal
fuses are blown. However, when OW is returned to Logic 0, the
position of the RDAC returns to the setting prior to the overwrite.
Because OW is not static, if the device is powered off and on,
the RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether the fuses had been
permanently set.
The remainder of the bits in the instruction byte are don’t cares
(see Figure 48 and Figure 49).
2
C-COMPATIBLE, 2-WIRE SERIAL BUS
Figure 49
).
2
C-compatible serial bus
Figure 48
Rev. H | Page 21 of 24
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 3).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from the write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, transitions on the
SDA line must occur during the low period of SCL and remain
stable during the high period of SCL (see Figure 50 and Figure 51).
Note that the channel of interest is the one that is previously
selected in write mode. If users need to read the RDAC values
of both channels, they must program the first channel in write
mode and then change to read mode to read the first channel
value. After that, the user must return to write mode with the
second channel selected and read the second channel value in
read mode. It is not necessary for users to issue the Frame 3
data byte in write mode for subsequent readback operations.
Refer to Figure 50 and Figure 51 for the programming format.
Following the data byte, the validation byte contains two valida-
tion bits, E0 and E1 (see Table 7). These bits signify the status of
the one-time programming (see Figure 50 and Figure 51).
After all data bits are read or written, the master establishes a
stop condition. A stop condition is defined as a low-to-high
transition on the SDA line while SCL is high. In write mode,
the master pulls the SDA line high during the 10
establish a stop condition (see Figure 48 and Figure 49). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master brings
the SDA line low before the 10
SDA line high to establish a stop condition (see Figure 50 and
Figure 51).
A repeated write function provides the user with the flexibility
of updating the RDAC output multiple times after addressing
and instructing the part only once. For example, after the RDAC
has acknowledged its slave address and instruction bytes in write
mode, the RDAC output is updated on each successive byte. If
different instructions are needed, however, the write/read mode
must restart with a new slave address, instruction, and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
th
clock pulse and then brings the
AD5172/AD5173
th
clock pulse to