AD5232BRU50-REEL7

Manufacturer Part NumberAD5232BRU50-REEL7
DescriptionIC DGTL POT DUAL 256POS 16-TSSOP
ManufacturerAnalog Devices Inc
AD5232BRU50-REEL7 datasheet
 


Specifications of AD5232BRU50-REEL7

Rohs StatusRoHS non-compliantTaps256
Resistance (ohms)50KNumber Of Circuits2
Temperature Coefficient600 ppm/°C TypicalMemory TypeNon-Volatile
Interface4-Wire SPI SerialVoltage - Supply2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case16-TSSOPResistance In Ohms50K
Number Of Elements2# Of Taps256
Resistance (max)50KOhmPower Supply RequirementSingle/Dual
Interface TypeSerial (4-Wire/SPI)Single Supply Voltage (typ)3/5V
Dual Supply Voltage (typ)±2.5VSingle Supply Voltage (min)2.7V
Single Supply Voltage (max)5.5VDual Supply Voltage (min)±2.25V
Dual Supply Voltage (max)±2.75VOperating Temp Range-40C to 85C
Operating Temperature ClassificationIndustrialMountingSurface Mount
Pin Count16For Use WithEVAL-AD5232-10EBZ - BOARD EVALUATION FOR AD5232-10
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SERIAL DATA INTERFACE
The AD5232 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS , and CLK) and uses a 16-bit serial data-word
that is loaded MSB first. The format of the SPI-compatible word
is shown in Table 7. The chip select ( CS ) pin must be held low
until the complete data-word is loaded into the SDI pin. When
CS returns high, the serial data-word is decoded according to
the instructions in Table 8. The command bits (Cx) control the
operation of the digital potentiometer. The address bits (Ax)
determine which register is activated. The data bits (Dx) are the
values that are loaded into the decoded register. Table 9 provides
an address map of the EEMEM locations. The last command
instruction executed prior to a period of no programming activity
should be the no operation (NOP) command instruction (Com-
mand Instruction 0). This instruction places the internal logic
circuitry in a minimum power dissipation state.
PR
VALID
COMMAND
COMMAND
PROCESSOR
AND ADDRESS
COUNTER
DECODE
CLK
SERIAL
REGISTER
CS
AD5232
SDI
Figure 33. Equivalent Digital Input/Output Logic
The AD5232 has an internal counter that counts a multiple of
16 bits (per frame) for proper operation. For example, the AD5232
works with a 16-bit or 32-bit word, but it cannot work properly
with a 15-bit or 17-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets if the count is not
a multiple of 4 when CS goes high, but the data remains in the
register if the count is a multiple of 4. In addition, the AD5232 has
a subtle feature whereby, if CS is pulsed without CLK and SDI,
the part repeats the previous command (except during power-
up). As a result, care must be taken to ensure that no excessive
noise exists in the CLK or CS line that may alter the effective
number of bits pattern.
The equivalent serial data input and output logic is shown in
Figure 33. The open-drain SDO is disabled whenever CS is logic
high. The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1; and CPHA = 0, CPOL = 0. CPHA and CPOL refer
to the control bits that dictate SPI timing in the following micro-
processors and MicroConverter® devices: the
ADuC824, the M68HC11, and the MC68HC16R1/916R1. ESD
protection of the digital inputs is shown in Figure 34 and Figure 35.
WP
5V
DAISY-CHAINING OPERATION
R
PULL-UP
The SDO pin serves two purposes: it can be used to read back
the contents of the wiper setting and the EEMEM using Command
Instruction 9 and Command Instruction 10 (see Table 8), or it can
SDO
be used for daisy-chaining multiple devices.The remaining com-
GND
mand instructions are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy chaining minimizes the number
of port pins required from the controlling IC (see Figure 36).
The SDO pin contains an open-drain N-channel FET that requires
a pull-up resistor if this function is used. As shown in Figure 36,
users must tie the SDO pin of one package to the SDI pin of the
next package. Users may need to increase the clock period because
the pull-up resistor and the capacitive loading at the SDO-to-SDI
interface may require additional time delay between subsequent
packages. If two AD5232s are daisy-chained, 32 bits of data are
required. The first 16 bits go to U2, and the second 16 bits with
the same format go to U1. The 16 bits are formatted to contain
the 4-bit instruction, followed by the 4-bit address, followed by
the eight bits of data. The CS pin should be kept low until all 32 bits
are locked into their respective serial registers. The CS pin is then
pulled high to complete the operation.
MicroConverter
ADuC812
and the
Rev. A | Page 15 of 24
V
DD
INPUTS
300Ω
LOGIC
PINS
AD5232
GND
Figure 34. Equivalent ESD Digital Input Protection
V
DD
INPUTS
300Ω
WP
AD5232
GND
Figure 35. Equivalent WP Input Protection
V
DD
AD5232
R
AD5232
P
2.2kΩ
U1
SDI
SDO
SDI
CS
CLK
CS
Figure 36. Daisy-Chain Configuration Using the SDO
AD5232
U2
SDO
CLK