DS3902U-530+T&R Maxim Integrated Products, DS3902U-530+T&R Datasheet - Page 9

• Manufacturer Part Number: DS3902U-530+T&R
• Description: IC DIGITAL RESISTER EEPROM 8USOP
• Manufacturer: Maxim Integrated Products

Specifications of DS3902U-530+T&R

• Taps: 256
• Resistance (ohms): 30K, 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resistance In Ohms: 30K, 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-3902T+530

Slave Address Byte: Each slave on the I
responds to a slave addressing byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7-bits
and the R/W bit in the least significant bit.
The DS3902’s slave address depends on the state of
the ADD_SEL pin. If ADD_SEL is low, then the slave
address byte is A2h, where the LSB is the R/W bit. If
the R/W bit is 0 (such as in A2h), then master indicates
it will write data to the slave. If R/W = 1 (A3h in this
case), the master will read data from the slave. If an
incorrect slave address is written, the DS3902 will
assume the master is communicating with another I
device and ignore the communication until the next
START condition is sent.
On the other hand, if the ADD_SEL pin is a logic high,
then the slave address byte is determined by the Slave
Address register saved in EEPROM (address 00h). The
LSB of the register is not used since it is in the bit loca-
tion of the R/W bit. Refer to the Slave Address and
ADD_SEL Pin section for more information.
Memory Address: During an I
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data and generate a STOP condition.
Remember the master must read the slave’s acknowl-
edgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
memory address, writes up to 2 data bytes and gener-
ates a STOP condition.
The DS3902 is capable of writing 1 or 2 bytes (1 page
or row) with a single write transaction. This is internally
controlled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 2-byte page.
Attempts to write to additional pages of memory without
sending a STOP condition between pages results in the
address counter wrapping around to the beginning of
the present row. Each row begins on even memory
addresses.
I
2
2
C Communication
C write operation, the
_____________________________________________________________________
2
Dual, NV, Variable Resistors
C bus
2
C
To prevent address wrapping from occurring, the mas-
ter must send a STOP condition at the end of the page,
and then wait for the bus free or EEPROM write time to
elapse. Then the master may generate a new START
condition, write the slave address byte (R/W = 0), and
the first memory address of the next memory row
before continuing to write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS3902 requires the EEPROM write time
(t
page to EEPROM. During the EEPROM write time, the
device will not acknowledge its slave address because
it is busy. It is possible to take advantage of that phe-
nomenon by repeated addressing the DS3902, which
allows the next page to be written as soon as the
DS3902 is ready to receive the data. The alternative to
acknowledge polling is to wait for maximum period of t
to elapse before attempting to write again to the device.
EEPROM Write Cycles: When EEPROM writes occur,
the DS3902 will write the whole EEPROM memory page
even if only a single byte on the page was modified.
Writes that do not modify all 2-bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified dur-
ing the transaction are still subject to a write cycle. This
can result in a whole page being worn out over time by
writing a single byte repeatedly. Writing a page one
byte at a time will wear the EEPROM out two times
faster than writing the entire page at once. The
DS3902’s EEPROM write cycles are specified in the
Nonvolatile Memory Characteristics table. The specifi-
cation shown is at the worst case temperature. It is
capable of handling approximately 10x that many
writes at room temperature.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation occurs
at the present value of the memory address counter. To
read a single byte from the slave the master generates a
START condition, writes the slave address byte with R/W =
1, reads the data byte with a NACK to indicate the end of
the transfer, and generates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates a
STOP condition.
W
) after the STOP condition to write the contents of the
with User EEPROM
W
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