CAT5140ZI-50-GT3 ON Semiconductor, CAT5140ZI-50-GT3 Datasheet
CAT5140ZI-50-GT3
Specifications of CAT5140ZI-50-GT3
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CAT5140ZI-50-GT3 Summary of contents
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CAT5140 Single Channel 256 Tap DPPt with Integrated 2 EEPROM and I The CAT5140 is a single channel non-volatile 256−tap digitally programmable potentiometer (DPPt). This DPP is comprised of a series of equal value resistor elements connected between two externally ...
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... Table 1. ORDERING INFORMATION Part Number Resistance CAT5140ZI−50−GT3 50 kW CAT5140ZI−00−GT3 100 kW †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 2. PIN FUNCTION DESCRIPTION Pin No. ...
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Table 5. POTENTIOMETER CHARACTERISTICS Parameter Potentiometer Resistance ‘−50’ Potentiometer Resistance ‘−00’ Potentiometer Resistance Tolerance Power Rating Wiper Current Wiper Resistance Integral Non−Linearity Differential Non−Linearity Integral Non−Linearity Differential Non−Linearity Voltage Resolution Zero Scale Error Full ...
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Table 7. CAPACITANCE (T = 25° 1.0 MHz Test Input/Output Capacitance (SDA) Input Capacitance (SCL, WP) Table 8. POWER UP TIMING (Notes 8 and 9) Parameter Power−up to Read Operation Power−up to Write Operation 8. This ...
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SCL SDA Start Condition LOW SCL t SU:STA t HD:STA SDA IN SDA OUT SCL from Master Data Output from Transmitter Data Output from Receiver Start Start SCL SDA IN t SU:WP WP Figure 2. Start and ...
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Device Operation The CAT5140 is a resistor array integrated with a I serial interface logic, an 8−bit volatile wiper register, and six 8−bit, non−volatile memory data registers. The resistor array contains 255 separate resistive elements connected in series. The physical ...
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STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non−volatile memory. If the STOP condition is not sent immediately after the last ACK the internal non−volatile ...
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... Address 1: Device ID (Read Only) Bit 7 defines the DPP device manufacturer; Catalyst/On Semiconductor = high (1) Bit 7 6 Name writing to address 1 has no effect. Attempts will return an ACK but no data will be written. Address 0: IVR/WR Register (I/O) Address 00h accesses one of two memory registers: the initial value register (IVR) or the wiper register (WR) depending upon the value of bit 7 in Access Control Register (ACR) which is at address 08h, above. WR controls the wiper’ ...
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Single write to either a volatile or non−volatile register. Note that Bit 7 of ACR determines which memory type is being written. Table 15. SINGLE WRITE (1) (2) Start Slave 0 Address R/W A single write to either a volatile ...
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E E1 TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O SYMBOL MIN A A1 ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...