CAT5140ZI-50-GT3 ON Semiconductor, CAT5140ZI-50-GT3 Datasheet - Page 6

• Manufacturer Part Number: CAT5140ZI-50-GT3
• Description: IC POT DPP NV 256TAP I2C 8MSOP
• Manufacturer: ON Semiconductor

Specifications of CAT5140ZI-50-GT3

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 100 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
serial interface logic, an 8−bit volatile wiper register, and six
8−bit, non−volatile memory data registers. The resistor
array contains 255 separate resistive elements connected in
series. The physical ends of the array are equivalent to the
fixed terminals of a mechanical potentiometer (R
The tap positions between and at the ends of the series
resistors are connected to the output wiper terminal (R
CMOS transistor switches. Only one tap point for the
potentiometer is connected to the wiper terminal at a time
and is determined by the value of an 8−bit Wiper Register
(WR).
to midscale; Wiper Register = 80h. When the power supply
becomes sufficient to read the non−volatile memory the
value stored in the Initial Value Register (IVR) is transferred
into the Wiper Register and the wiper moves to this new
position. Five additional 8−bit non−volatile memory data
registers are provided for general purpose data storage. Data
can be read or written to the volatile or the non−volatile
memory data registers via the I
Serial Bus Protocol
protocol:
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5140 will be considered a slave device
in all applications.
The CAT5140 is a resistor array integrated with a I
When power is first applied to CAT5140 the wiper is set
The following defines the features of the 2−wire bus
The device controlling the transfer is a master, typically a
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
FEh
FFh
80h
01h
00h
2
C bus.
R
R
R
W
H
L
H
and R
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W
) by
2
L
C
).
6
START Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5140 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
START condition. The Master then sends the address of the
particular slave device it is requesting. CAT5140 has a fixed
7 bit slave address: 0101000. The 8
Read/Write instruction bit. For a Read the value is “1” and
for Write the value is “0”.
address byte, the CAT5140 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge (ACK)
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
a START condition and its slave address. If the device has
been selected along with a write operation, it responds with
an acknowledge after receiving each 8−bit byte. When the
CAT5140 is in a READ mode it transmits 8 bits of data,
releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5140 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
WRITE Operation
condition and the slave address information to the Slave
device. In CAT5140’s case the slave address also contains a
Read/Write command (R/W) on the last bit of the 1st byte.
After receiving an acknowledge from the Slave, the Master
device transmits a second byte containing a Memory
Address to select an available register. After a second
acknowledge is received from the Slave, the Master device
sends the data to be written into the selected register. The
CAT5140 acknowledges once more and the Master
Table 12. SALVE ADDRESS BIT FORMAT
The START condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
The bus Master begins a transmission by sending a
After the Master sends a START condition and the slave
After a successful data transfer, each receiving device is
CAT5140 responds with an acknowledge after receiving
In the Write mode, the Master device sends the START
MSB
0
1
0
1
0
th
0
bit (LSB) is the
0
LSB
R/W