DS3906U+T&R Maxim Integrated Products, DS3906U+T&R Datasheet - Page 10

• Manufacturer Part Number: DS3906U+T&R
• Description: IC RESIST VAR TRPL 10USOP
• Manufacturer: Maxim Integrated Products

Specifications of DS3906U+T&R

• Taps: 64
• Resistance (ohms): 1.45K, 2.54K, 2.54K
• Number Of Circuits: 3
• Temperature Coefficient: 60 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 1.45K, 2.54K, 2.54K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Triple NV Low Step Size Variable
Resistor Plus Memory
Using an external resistor in parallel with any of the
DS3906’s resistors makes the effective resistance linear
with small increments from position to position. Typical
values for the external resistors are 87Ω for Resistor 0
and 1 and 258Ω for Resistor 2. The effective resistance
will be the most linear when these values are used. Of
course these values may be tweaked to achieve the
desired step size and range. The effects of changing
R
resistor may be used to further customize the desired
response. If the DS3906’s transfer function does not
meet the applications needs, contact the factory at the
email address provided on the front page to inquire
about custom resistance values.
The DS3906’s I
state of the A0, A1, and A2 address pins as shown in
Figure 1. DS3906 Slave Address Byte
Figure 2. I
10
EXT
SDA
SCL
NOTE: TIMING IS REFERENCE TO V
____________________________________________________________________
is shown on the front page. Likewise, a series
*THE SLAVE ADDRESS IS DETERMINED BY
STOP
MSB
ADDRESS PINS A0, A1, AND A2.
2
I
C Timing Diagram
2
1
C Slave Address and Address Pins
t
BUF
0
2
START
C slave address is determined by the
1
ADDRESS*
SLAVE
Selection/Considerations
IL(MAX)
0
t
t
HD:STA
LOW
AND V
A2
IH(MIN)
External Resistor
A1
.
t
R
t
A0
HD:DAT
READ/WRITE
R/W
BIT
LSB
t
F
t
HIGH
t
SU:DAT
Figure 1. Address pins tied to GND result in a ‘0’ in the
corresponding bit position in the slave address.
Conversely, address pins tied to V
the corresponding bit positions. I
described in detail in the following section.
The following terminology is commonly used to
describe I
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic high states. When the bus is idle it often initi-
ates a low power mode for slave devices.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
REPEATED
START
2
C data transfers.
t
SU:STA
t
HD:STA
I
2
C Serial Interface
2
t
C communication is
SP
CC
Description
I
2
C Definitions
result in a ‘1’ in
t
SU:STO