CY7C1412KV18-250BZXC Cypress Semiconductor Corp, CY7C1412KV18-250BZXC Datasheet - Page 10

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CY7C1412KV18-250BZXC

Manufacturer Part Number
CY7C1412KV18-250BZXC
Description
CY7C1412KV18-250BZXC
Manufacturer
Cypress Semiconductor Corp
Series
-r
Datasheet

Specifications of CY7C1412KV18-250BZXC

Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
36M (2M x 18)
Speed
250MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
CY7C1412KV18-250BZXC
Manufacturer:
CYPRESS
Quantity:
455
Part Number:
CY7C1412KV18-250BZXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
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Part Number:
CY7C1412KV18-250BZXC
Manufacturer:
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Quantity:
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Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the QDR II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
Switching Characteristics on page
Application Example
Figure 1
Document Number: 001-57825 Rev. *D
MASTER
ASIC)
(CPU
BUS
or
shows two QDR II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Source K#
Delayed K
Source K
DATA IN
Address
WPS#
BWS#
RPS#
Vt
R
R
R = 50ohms
25.
D
A
R
P
S
#
Vt = Vddq/2
W
P
S
#
SRAM #1
Figure 1. Application Example
W
B
S
#
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
PLL
These chips use a PLL which is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time).
CY7C1410KV18, CY7C1425KV18
CY7C1412KV18, CY7C1414KV18
D
A
R
Vt
Vt
R
P
#
S
W
P
S
#
W
B
S
#
SRAM #2
C C#
CQ/CQ#
K
ZQ
K#
Q
Page 10 of 32
R = 250ohms
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