CY7C1412KV18-250BZCT Cypress Semiconductor Corp, CY7C1412KV18-250BZCT Datasheet

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... To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words (CY7C1410KV18), 9-bit words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or 36-bit words (CY7C1414KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the ...

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... D [8:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Write Write Address Reg Reg Register Control Logic Read Data Reg Reg. Reg. 8 Reg. Write Write Address Reg Reg Register ...

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... Logic Block Diagram (CY7C1412KV18 [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1414KV18 [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 ...

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... TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 TAP Electrical Characteristics ...................................... 16 Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 TAP AC Switching Characteristics ............................... 17 TAP Timing and Test Conditions .................................. 17 Identification Register Definitions ................................ 18 Scan Register Sizes ....................................................... 18 Instruction Codes ........................................................... 18 Boundary Scan Order .................................................... 19 Power Up Sequence in QDR II SRAM ...

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... Pin Configuration The pin configurations for CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow NC/72M DOFF V V REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Note 1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configurations for CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...

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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized × arrays each × 8) for CY7C1410KV18 × arrays each × 9) for CY7C1425KV18 × arrays each × 18) for CY7C1412KV18, and 1 M × arrays each of 512 K × 36) for CY7C1414KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1410KV18 and CY7C1425KV18, 20 address inputs for CY7C1412KV18, and 19 address inputs for CY7C1414KV18 ...

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... Ground Ground for the device Power supply Power supply inputs for the outputs of the device. DDQ Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Pin Description Switching Characteristics on page 25. Switching Characteristics on page 25. output impedance are set to 0.2 x RQ, where resistor [x:0] ...

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... K clock rise. Depth Expansion The CY7C1412KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port using select input can deselect the specified port ...

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... Delayed 50ohms Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 PLL These chips use a PLL which is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum ...

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... Truth Table The truth table for CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. Operation Write cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...

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... X = “Don't Care,” Logic HIGH Logic LOW, 10. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 [9, 10] [9, 10] K – ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 16 ...

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... Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 [11] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 13. Overshoot: V (AC) < 0.85 V (Pulse width less than t IH DDQ 14. All voltage referenced to Ground. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 0 Bypass Register Instruction Register ...

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... CS CH 16. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Description [16] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50 ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Value CY7C1425KV18 CY7C1412KV18 000 000 11010011010001111 11010011010010111 ...

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... Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... DDQ DOFF Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 PLL Constraints PLL uses K clock as its synchronizing input. The input must ■ have low phase jitter, which is specified as t The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the ■ ...

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... OL DDQ 22. V (min whichever is larger, V REF DDQ Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Neutron Soft Error Immunity Parameter LSBU LMBU DD + 0.5 V DDQ + 0.5 V SEL LMBU or SEL events occurred during testing; this column represents a 2 statistical  ...

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... Over the Operating Range Parameter Description [23 operating supply DD DD Note 23. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Test Conditions V = Max, 333 MHz (× mA, OUT (× 1/t MAX CYC (× 18) (× ...

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... Over the Operating Range Parameter Description V Input HIGH voltage IH V Input LOW voltage IL Note 24. Overshoot: V (AC) < 0.85 V (Pulse width less than t IH DDQ Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Test Conditions Max V , 333 MHz (× both ports deselected, (× 9)  V  ...

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... Note 25. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0. 250 pulse levels of 0. 1.25 V, and output loading of the specified I Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Test Conditions = 25  MHz 1 ...

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... This part has a voltage regulator internally; t POWER Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 333 MHz 300 MHz Min Max Min Max Min Max Min Max Min Max [28] 1 – ...

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... For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock µs (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 333 MHz 300 MHz Min Max Min Max Min Max Min Max Min Max – ...

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... Outputs are disabled (high Z) one clock cycle after a NOP. 35. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 WRITE READ WRITE ...

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... CY 7C 14XX K V18 - XXX BZ X Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 www.cypress.com Package Diagram Package Type 51-85180 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) 51-85180 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free 165-ball Fine-pitch Ball Grid Array (13 × ...

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... Package Diagram Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. -0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

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... TCK test clock TMS test mode select TDI test data-in TDO test data-out TQFP thin quad flat pack Document Number: 001-57825 Rev. *D CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Document Conventions Units of Measure Symbol Unit of Measure  ohms % percent µs micro seconds ms milli seconds ...

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... Document History Page Document Title: CY7C1410KV18/CY7C1425KV18/CY7C1412KV18/CY7C1414KV18, 36-Mbit QDR Architecture Document Number: 001-57825 Orig. of Submission Rev. ECN No. Change Date ** 2816620 VKN/AESA 11/27/2009 New Data Sheet *A 2884865 VKN 02/26/2010 Changed t *B 3018546 NJY 10/21/2010 Converted from Preliminary to Final. *C 3155124 VIDB 01/27/2011 Added Note 32. ...

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... QDR registered trademark of Cypress Semiconductor Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 cypress.com/go/plc Revised February 25, 2011 PSoC Solutions psoc ...