CY7C1412KV18-250BZCT Cypress Semiconductor Corp, CY7C1412KV18-250BZCT Datasheet - Page 8

• Manufacturer Part Number: CY7C1412KV18-250BZCT
• Description: CY7C1412KV18-250BZC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1412KV18-250BZCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-57825 Rev. *D
Pin Name
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC /72M
NC /144M
NC /288M
V
V
V
V
REF
DD
SS
DDQ
Power supply Power supply inputs to the core of the device.
Power supply Power supply inputs for the outputs of the device.
Echo clock
Echo clock
reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
Input
N/A
I/O
(continued)
CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the
echo clocks is shown in
CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the
echo clocks is shown in the
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
connected between ZQ and ground. Alternatively, connect this pin directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL turn off  active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,
connect this pin to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the device.
Switching Characteristics on page
Switching Characteristics on page
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor
Pin Description
CY7C1410KV18, CY7C1425KV18
CY7C1412KV18, CY7C1414KV18
25.
25.
DDQ
, which enables the
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