DS1845E-050+T&R Maxim Integrated Products, DS1845E-050+T&R Datasheet

IC POT/MEM DUAL NV 50K 14-TSSOP

DS1845E-050+T&R

Manufacturer Part Number
DS1845E-050+T&R
Description
IC POT/MEM DUAL NV 50K 14-TSSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1845E-050+T&R

Taps
100, 256
Resistance (ohms)
10K, 50K
Number Of Circuits
2
Temperature Coefficient
750 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Resistance In Ohms
10K and 50K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
§ Two linear taper potentiometers
§ 256 bytes of EEPROM memory
§ Access to data and potentiometer control via
§ External Write Enable pin to protect data and
§ Nonvolatile wiper storage
§ Operates from 3V or 5V supplies
§ Packaging: Flip Chip Package, 16-ball
§ Industrial operating temperature: -40ºC to
DESCRIPTION
The DS1845 Dual NV Potentiometer and Memory consists of one 100-position linear taper
potentiometer, one 256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire
interface.
applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration
or calibration data for a specific system or device as well as provide control of the potentiometer wiper
settings. Any type of user information may reside in the first 248 bytes of this memory. The next two
addresses of EEPROM memory are for potentiometer settings. Access to this EEPROM is via an
industry standard 2-wire bus. The wiper position of the DS1845, as well as EEPROM data, can be
hardware write-protected using the Write Protect (WP) input pin. Up to eight DS1845s can be installed
on a single 2-wire bus. Access to an individual device is achieved by using a device address that is
determined by the logic levels of address pins A0 though A2. Additionally, the DS1845 will operate
from 3 volt or 5 volt supplies. Three package options are available: Flip Chip Package, 16-ball CSBGA
and 14-pin TSSOP.
www.maxim-ic.com
- DS1845-010 one 10k, 100 position &
- DS1845-050 one 10k, 100 position &
- DS1845-100 one 10k, 100 position &
an I
potentiometer settings
CSBGA, 14-pin TSSOP
+85ºC
one 10k, 256 position
one 50k, 256 postition
one 100k, 256 position
2
C compatible 2-wire interface
The device provides an ideal method for setting bias voltages and currents in control
1 of 14
14-Pin Flip Chip (100-mil x 100-mil) (Not Shown)
SCL
SDA
GND
A0
A1
A2
WP
16-Ball CSBGA (4mm x 4mm)
A
B
C
D
14-Pin TSSOP (173 mil)
1
1
2
3
4
5
6
7
Dual NV Potentiometer
Top View
2
3
14
13
12
11
10
9
8
4
Vcc
H0
W1
H1
L1
W0
L0
and Memory
DS1845
011006

Related parts for DS1845E-050+T&R

DS1845E-050+T&R Summary of contents

Page 1

FEATURES § Two linear taper potentiometers - DS1845-010 one 10k, 100 position & one 10k, 256 position - DS1845-050 one 10k, 100 position & one 50k, 256 postition - DS1845-100 one 10k, 100 position & one 100k, 256 position ...

Page 2

PIN DESCRIPTIONS Name TSSOP BGA GND 7 D1 SDA 1 B2 SCL ...

Page 3

DS1845 BLOCK DIAGRAM Figure 1 VCC 2-WIRE INTERFACE GND SDA SCL MEMORY ORGANIZATION The DS1845’s serial EEPROM is internally organized with 256 words of 1 byte each. Each word requires an 8-bit address for random word ...

Page 4

Interface Reset: After any interruption in protocol, power loss, or system reset, the following steps reset the DS1845. 1. Clock up to nine cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a ...

Page 5

CURRENT ADDRESS READ The DS1845 has an internal address register that maintains the address used during the last read or write operation, incremented by one. This data is maintained as long as V address was the last byte in memory, ...

Page 6

Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH defines a START condition. Stop data transfer: A change in the state of the data line from LOW to ...

Page 7

The DS1845 may operate in the following two modes: 1. Slave receiver mode: Serial data and clock are received through SDA and SCL respectively. After each byte is received, an acknowledge bit is transmitted. recognized as the beginning and end ...

Page 8

WIRE PROTOCOL DATA TRANSFER PROTOCOL Figure 2 2-WIRE AC CHARACTERISTICS Figure ...

Page 9

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Programming Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...

Page 10

DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Current I Active Input Leakage Wiper Resistance Wiper Current Input Logic levels A0, A1, A2 Input Current each I/O pin I Standby Current STBY 3V 5V Low Level Output V Voltage ...

Page 11

ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; V PARAMETER SYMBOL End-to-End Resistance Absolute Linearity Relative Linearity -3dB Cutoff freq. f CUTOFF End-to-End Temp. Coefficient CONDITION MIN 25 C -20 ° -0.75 10kW/100 pos. 10kW/256 pos. -0.75 20kW/256 pos. -1.0 50kW/256 pos. ...

Page 12

AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL SCL clock frequency Bus free time between STOP and START condition Hold time (repeated) START condition Low period of SCL clock High period of SCL clock Data hold time Data set-up time Start set-up time ...

Page 13

total capacitance of one bus line in picofarads. Timing referenced to 0.9V 8. EEPROM write begins after a stop condition occurs. 9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position. ...

Page 14

... DS1845B-010+T&R 16 BALL CSBGA/T&R LF (4X4 DS1845B-010/T&R DS1845B-100+ 16 BALL CSBGA LF (4X4 MM) DS1845E-100+T&R 14 PIN TSSOP/T&R LF (173 DS1845B-010+ 16 BALL CSBGA LF (4X4 MM) DS1845E-010+ 14 PIN TSSOP LF (173 MIL) DS1845E-010+T&R DS1845E-050+T&R 14 PIN TSSOP/T&R LF (173 DS1845B-050+ 16 BALL CSBGA LF (4X4 MM) DS1845E-050+ DS1845B-020 16 BALL CSBGA (4X4 MM) DS1845B-050/T&R DS1845B-050+T&R 16 BALL CSBGA/T&R LF (4X4 ...

Related keywords