DS1844S-100+T&R Maxim Integrated Products, DS1844S-100+T&R Datasheet - Page 3

• Manufacturer Part Number: DS1844S-100+T&R
• Description: IC POT DIG QUAD 100K 20-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS1844S-100+T&R

• Taps: 64
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Volatile
• Interface: 2-Wire or 5-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When writing data, the R/
latched (or valid) on the low-to-high transition of the CLK signal. Once, eight low-to-high transitions
have occurred on the CLK input, the associated 8-bit data block will be loaded as the wiper’s value on the
falling edge of the eighth clock pulse. Potentiometer wiper values can be loaded in any order. Also,
potentiometer wiper data can be loaded 1, 2, 3, or 4 bytes at a time. When
low, the 5-wire port will be disabled.
While
inhibited; preventing the passing of data from D
directly from D
When reading data, the R/
clocked out of the device and will appear on the D
edge of a clock pulse after a maximum time period of 20 ns (of that falling edge). Data will appear on
D
so forth.
2-Wire Addressable Serial Port Control
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device which generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1844 operates as
a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The 2-wire serial port is selected when the port select input, PS, is in a high-state. The following I/O
terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2, PS=1. Timing diagrams for the 2-wire
serial port can be found in Figures 4 through 8. Timing information for the 2-wire serial port is provided
in the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined (See Figure 4).
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
OUT
-
-
most significant bit (MSB) first and starting with potentiometer-0, followed by potentiometer-1 and
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high will be interpreted as control signals.
RST
is high and R/
IN
to D
OUT
W
.
W
W
input should be in a low state. Once
input should be in a high state. Once
is low, (the write or load state) the cascade data output, D
3 of 14
IN
to D
OUT
OUT
terminal. A data bit will be valid on the falling
. However, when
RST
RST
has activated the port, a data bit is
has enabled the port, data can be
RST
RST
transitions from high to
is low data is passed
OUT
will be