LTC2604IGN-1#PBF Linear Technology, LTC2604IGN-1#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC2604IGN-1#PBF
• Description: IC DAC 16BIT QUAD R-R 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2604IGN-1#PBF

• Settling Time: 10µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 10mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Number Of Channels: 4
• Resolution: 16b
• Interface Type: SERIAL 3W SPI UW
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Single
• Output Type: Voltage
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATION
Power Supply Sequencing
The voltage at REF (Pins 3, 6, 12 and 15) should be kept
within the range – 0.3V ≤ REF x ≤ V
lute Maximum Ratings). Particular care should be taken
to observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
in transition.
Transfer Function
The digital-to-analog transfer function is
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REF x is the voltage at REF
A, REF B, REF C and REF D (Pins 3, 6, 12 and 15).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded fi rst; then the 4-bit
DAC address, A3-A0; and fi nally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
INPUT WORD (LTC2604)
INPUT WORD (LTC2614)
INPUT WORD (LTC2624)
V
OUT(IDEAL)
C3
C3
C3
COMMAND
COMMAND
COMMAND
C2
C2
C2
=
C1 C0
C1 C0
C1 C0
2
k
N
[REF x – REFLO]+REFLO
A3
A3
A3
ADDRESS
ADDRESS
ADDRESS
A2
A2
A2
A1
A1
A1
CC
A0
A0
A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
+ 0.3V (see Abso-
MSB
MSB
MSB
D15
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
CC
(Pin 16) is
D14
D13
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
DATA (12 BITS + 4 DON’T-CARE BITS)
Table 1.
COMMAND*
ADDRESS (n)*
*Command and address codes not shown are reserved and should not
(LTC2604, LTC2614 and LTC2624 respectively). Data can
only be transferred to the device when the CS/LD signal
is low. The rising edge of CS/LD ends the data transfer
and causes the device to carry out the action specifi ed in
the 24-bit input word. The complete sequence is shown
in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The fi rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
DATA (14 BITS + 2 DON’T-CARE BITS)
be used.
C3
A3
0
0
0
0
0
1
0
0
0
0
1
LTC2604/LTC2614/LTC2624
C2
A2
0
0
0
0
1
1
0
0
0
0
1
DATA (16 BITS)
C1
A1
0
0
1
1
0
1
0
0
1
1
1
C0
A0
0
1
0
1
0
1
0
1
0
1
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
DAC A
DAC B
DAC C
DAC D
All DACs
D1 D0
LSB
D1 D0
X
LSB
X
D1 D0
X
X
2604 TBL03
2604 TBL01
2604 TBL02
LSB
X
X
11
2604fd