MAX5873EGK+D Maxim Integrated Products, MAX5873EGK+D Datasheet - Page 4

• Manufacturer Part Number: MAX5873EGK+D
• Description: IC DAC 12BIT 200MSPS DUAL 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5873EGK+D

• Settling Time: 14ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Conversion Rate: 200 MSPs
• Resolution: 12 bit
• Interface Type: Parallel
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
50Ω double terminated, transformer-coupled output, I
= +25°C.) (Note 2)
4
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time
Output Rise Time
Output-Voltage Settling Time
Output Propagation Delay
Glitch Impulse
Output Noise
TIMING CHARACTERISTICS
Data to Clock Setup Time
Data to Clock Hold Time
Single-Port (Interleaved Mode)
Data Latency
Dual-Port (Parallel Mode) Data
Latency
Minimum Clock Pulse-Width High
Minimum Clock Pulse-Width Low
CMOS LOGIC INPUTS (A11/B11–A0/B0, XOR, SELIQ, PD, TORB, DORI)
Input Logic High
Input Logic Low
Input Leakage Current
PD, TORB, DORI Internal
Pulldown Resistance
Input Capacitance
CLOCK INPUTS (CLKP, CLKN)
Differential Input
Voltage Swing
Differential Input Slew Rate
External Common-Mode Voltage
Range
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
DD3.3
_______________________________________________________________________________________
= DV
PARAMETER
DD3.3
= AV
CLK
= 3.3V, AV
SYMBOL
AV
AV
t
t
SR
SETTLE
t
V
N
SETUP
C
t
R
t
HOLD
DD1.8
FALL
RISE
t
V
C
t
t
V
COM
I
DD3.3
DD1.8
OUT
CH
CLK
CLK
PD
CL
IN
CLK
IH
IL
IN
= DV
90% to 10% (Note 5)
10 % to 90% (Note 5)
Output settles to 0.025% FS (Note 5)
Excluding data latency (Note 5)
Measured differentially
I
I
Referenced to rising edge of clock (Note 6)
Referenced to rising edge of clock (Note 6)
Latency to I output
Latency to Q output
CLKP, CLKN
CLKP, CLKN
V
Sine wave
Square wave
(Note 7)
OUTFS
OUTFS
PD
DD1.8
OUTFS
= V
= 2mA
= 20mA
TORB
= 1.8V, GND = 0, f
= 20mA, T
= V
CONDITIONS
DORI
A
= T
= 3.3V
MIN
CLK
to T
= f
MAX
DAC
, unless otherwise noted. Typical values are at T
, external reference V
DV
3.135
1.710
0.7 x
MIN
-0.6
2.1
DD3.3
AV
REFIO
> 100
> 1.5
> 0.5
TYP
±0.3
-1.2
CLK
0.7
0.7
1.1
1.5
5.5
2.4
2.4
1.5
2.5
2.5
3.3
1.8
14
30
30
1
9
8
1
5
/ 2
= 1.25V, output load
DV
3.465
1.890
MAX
0.3 x
DD3.3
20
pA/√Hz
UNITS
cycles
cycles
Clock
Clock
pV
V
V/µs
MΩ
µA
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
P-P
V
V
V
V
•
s
A