CS4354-CSZ Cirrus Logic Inc, CS4354-CSZ Datasheet - Page 13

• Manufacturer Part Number: CS4354-CSZ
• Description: IC DAC 24BIT SRL 14SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4354-CSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 65mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 Ksps
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Power Dissipation: 65 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Number Of Dacs: 2
• Output Voltage: 5 V
• Power Consumption: 50 mW
• Supply Current: 5 V
• Thd Plus Noise: - 86 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1808; CS4354-CSZ

DS895A2
4. APPLICATIONS
4.1
4.2
4.3
Ground-Centered Line Outputs
An on-chip charge pump creates a negative supply which allows the full-scale output swing to be centered
around ground. This eliminates the need for large DC-blocking capacitors which create audible pops at pow-
er-on and provides improved low frequency response. See the
complete specifications of the full-scale output voltage. It should be noted that external output impedance
between the AOUTx pin and the load will lower the voltage delivered to the load.
Sample Rate Range/Operational Mode Detect
The CS4354 operates in one of three operational modes. The device will auto-detect the correct mode when
the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in
Table
LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device
for speed mode auto-detection; see
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in
Refer to
to
LRCK
Mode
(kHz)
176.4
“Switching Specifications - Serial Audio Interface” on page 8
44.1
88.2
192
32
48
96
3. Sample rates outside the specified range for each mode are not supported. In addition to a valid
Section 4.6
12.2880
22.5792
24.5760
11.2896
Input Sample Rate (Fs)
128x
-
-
-
170 kHz - 216 kHz
84 kHz - 108 kHz
30 kHz - 54 kHz
for the required SCLK timing associated with the selected Digital Interface Format and
Table 4. Common MCLK and LRCK Frequencies
Table 3. CS4354 Operational Mode Auto-Detect
16.9344
18.4320
33.8688
36.8640
QSM
192x
-
-
-
Figure
12.2880
22.5792
24.5760
45.1584
49.1520
11.2896
8.1920
256x
9.
MCLK (MHz)
12.2880
16.9344
18.4320
33.8688
36.8640
384x
-
-
DSM
for the maximum allowed clock frequencies.
DAC Analog Characteristics
16.3840
22.5792
24.5760
45.1584
49.1520
512x
Double-Speed Mode
Single-Speed Mode
Quad-Speed Mode
-
-
Mode
Table 4 on page
24.5760
33.8688
36.8640
768x
-
-
-
-
SSM
table for the
13.
CS4354
32.7680
45.1580
49.1520
1024x
-
-
-
-
13