MAX5874EGK+D Maxim Integrated Products, MAX5874EGK+D Datasheet - Page 15

• Manufacturer Part Number: MAX5874EGK+D
• Description: IC DAC 14BIT 200MSPS DUAL 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5874EGK+D

• Settling Time: 14ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified. For a
DAC, the deviations are measured at every individual
step.
Differential nonlinearity is the difference between an actu-
al step height and the ideal value of 1 LSB. A DNL error
specification of less than 1 LSB guarantees a monoton-
ic transfer function.
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Dynamic Performance Parameter Definitions
Static Performance Parameter Definitions
14-Bit, 200Msps, High-Dynamic-Performance,
SNR = 6.02 x N + 1.76
______________________________________________________________________________________
Differential Nonlinearity (DNL)
Signal-to-Noise Ratio (SNR)
Integral Nonlinearity (INL)
Offset Error
Gain Error
Dual DAC with CMOS Inputs
The DAC output noise floor is the sum of the quantiza-
tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal components) to the RMS value
of their next-largest distortion component. SFDR is usual-
ly measured in dBc and with respect to the carrier fre-
quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR is
observed within a predefined window or to Nyquist.
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone.
Commonly used in combination with wideband code-
division multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
A glitch is generated when a DAC switches between two
codes. The largest glitch is usually generated around the
midscale transition, when the input pattern transitions from
011...111 to 100...000. The glitch impulse is found by inte-
grating the voltage of the glitch at the midscale transition
over time. The glitch impulse is usually specified in pV
Adjacent Channel Leakage Power Ratio (ACLR)
Two-Tone Intermodulation Distortion (IMD)
Spurious-Free Dynamic Range (SFDR)
Noise Spectral Density
Glitch Impulse
Settling Time
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