MAX5888AEGK+D Maxim Integrated Products, MAX5888AEGK+D Datasheet - Page 15

• Manufacturer Part Number: MAX5888AEGK+D
• Description: IC DAC 16BIT 3.3V 500MSPS 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5888AEGK+D

• Settling Time: 11ns
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 130mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11. GSM/EDGE Tx Mask
Grounding and power-supply decoupling can strongly
influence the performance of the MAX5888. Unwanted
digital crosstalk may couple through the input, refer-
ence, power supply, and ground connections, affecting
dynamic performance. Proper grounding and power-
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed. This
reduces EMI and internal crosstalk that can significant-
ly affect the dynamic performance of the MAX5888.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should run on lines directly
above the ground plane. Since the MAX5888 has sepa-
rate analog and digital ground buses (AGND,
CLKGND, and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two planes.
Digital signals should be run above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Digital signals should be kept as far
away from sensitive analog inputs, reference inputs
sense lines, common-mode input, and clock inputs as
Performance DAC with Differential LVDS Inputs
Grounding, Bypassing, and Power-Supply
-30
-60
-70
-73
-75
-80
-90
O
0.2 0.4 0.6
FREQUENCY OFFSET FROM CARRIER (MHz)
______________________________________________________________________________________
MEASUREMENT BANDWIDTH
1.2
30kHz 100kHz
1.8
3.3V, 16-Bit, 500Msps High Dynamic
6.0
Considerations
IMD REQUIREMENT: < -70dBc
INBAND
OUTBAND
WORST-CASE
NOISE LEVEL
practical. A symmetric design of clock input and ana-
log output lines is recommended to minimize 2nd-order
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5888 supports three separate power-supply
inputs for analog (AVDD), digital (DVDD), and clock
(VCLK) circuitry. Each AVDD, DVDD, and VCLK input
should at least be decoupled with a separate 0.1µF
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 13). Try to
minimize the analog and digital load capacitances for
optimized operation. All three power-supply voltages
should also be decoupled at the point they enter the
PC board with tantalum or electrolytic capacitors.
Ferrite beads with additional decoupling capacitors
forming a pi network could also improve performance.
The analog and digital power-supply inputs AV
VCLK, and DV
age range of 3.3V ±5%.
Figure 12. 4-Tone MTPR Test Results, f
f
CLK
= 300MHz
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
26
4-TONE MULTITONE POWER RATIO PLOT
(f
f
f
f
f
T1
T2
T3
T4
CLK
A
BW = 12MHz
DD
OUT
= 30.0659MHz
= 31.0181MHz
= 33.0688MHz
= 34.0209MHz
= 300MHz, f
28
= -12dB FS
of the MAX5888 allow a supply volt-
f
T1
30
f
OUT
f
T2
CENTER
32
(MHz)
f
T3
= 31.9702MHz)
34
f
CENTER
T4
36
= 31.97MHz,
38
DD
15
,