LTC2629IGN#TRPBF Linear Technology, LTC2629IGN#TRPBF Datasheet - Page 5

no-image

LTC2629IGN#TRPBF

Manufacturer Part Number
LTC2629IGN#TRPBF
Description
IC DAC 12BIT R-R QUAD 16SSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC2629IGN#TRPBF

Settling Time
7µs
Number Of Bits
12
Data Interface
Serial
Number Of Converters
4
Voltage Supply Source
Single Supply
Power Dissipation (max)
750µW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC2629IGN#TRPBFLTC2629IGN
Manufacturer:
LT
Quantity:
10 000
Company:
Part Number:
LTC2629IGN#TRPBFLTC2629IGN#PBF
Manufacturer:
Linear Technology
Quantity:
135
Company:
Part Number:
LTC2629IGN#TRPBFLTC2629IGN#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC2629IGN#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC2629IGN#TRPBFLTC2629IGN-1
Manufacturer:
LT
Quantity:
10 000
timing characteristics
SYMBOL
V
f
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code k
2
rounded to the nearest whole code. For V
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or V
Note 4: Inferred from measurement at code kL (see Note 2) and at full-Scale.
Note 5: V
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
range, otherwise specifications are at T
SCL
HD(STA)
LOW
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
f
SU(STO)
BUF
1
2
N
CC
– 1, where N is the resolution and k
= 2.7V to 5.5V
CC
= 5V, V
PARAMETER
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
Data Set-Up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
LDAC Low Pulse Width
REF
= 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
CC
, CA0, CA1 and CA2 floating.
L
is given by k
REF
= 4.096V and N = 16, k
A
= 25°C. (See Figure 1) (Notes 8, 9)
L
= 0.016(2
The
L
to code
l
N
/V
denotes the specifications which apply over the full operating temperature
REF
L
CONDITIONS
(Note 7)
(Note 7)
=
),
Note 6: V
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: C
Note 8: All values refer to V
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
Note 10: DC crosstalk is measured with V
= REFD = 4.096V, with the measured DAC at mid-scale, unless otherwise
noted.
Note 11: R
Note 12: Guaranteed by design and not production tested.
LTC2609/LTC2619/LTC2629
CC
B
L
= capacitance of one bus line in pF.
= 5V, V
= 2kΩ to GND or V
REF
l
l
l
l
l
l
l
l
l
l
l
l
l
= 4.096V. DAC is stepped ±1LSB between half scale
20 + 0.1C
20 + 0.1C
IH(MIN)
MIN
100
400
0.6
1.3
0.6
0.6
0.6
1.3
20
0
0
CC
.
and V
B
B
IL(MAX)
CC
TYP
= 5V, REFA = REFB = REFC
levels.
MAX
400
300
300
0.9
26091929fb
UNITS

kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns

Related parts for LTC2629IGN#TRPBF