CS43L42-KZZ Cirrus Logic Inc, CS43L42-KZZ Datasheet
CS43L42-KZZ
Specifications of CS43L42-KZZ
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CS43L42-KZZ Summary of contents
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... V supply with the line amplifier powered-down. These features are ideal for portable CD, MP3 and MD players and other portable playback systems that require extremely low power consumption. ORDERING INFORMATION CS43L42-KZ CS43L42-KZZ, Lead Free CDB43L42 Control Port ∆Σ Digital Volume DAC ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS43L42 ............................... 22 DS481PP2 ...
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... Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3 ............................. 35 Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4 ............................. 35 Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5 ............................. 35 Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6 ............................. 36 Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0 ............................. 36 DS481PP2 ...
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... Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format 1 ............................. 36 Figure 28. CS43L42 Stand Alone Mode - Serial Audio Format 2 ............................. 37 Figure 29. CS43L42 Stand Alone Mode - Serial Audio Format 3 ............................. 37 Figure 30. De-Emphasis Curve ................................................................................. 38 Figure 31. ATAPI Block Diagram .............................................................................. 38 LIST OF TABLES Table 1. Example Analog Volume Settings ............................................................... 18 Table 2 ...
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... Base-rate Mode Symbol Min (Note 1) unweighted TBD A-Weighted TBD unweighted - A-Weighted - (Note 1) THD - - - - kHz) - (Note 1) unweighted TBD A-Weighted TBD unweighted - A-Weighted - (Note 1) THD - - - - kHz) - CS43L42 = 16 Ω (see Fig High-Rate Mode Typ Max Min Typ 91 - TBD TBD -80 TBD - -80 - -69 - -29 - -78 - -67 - -27 100 - - ...
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... Base-rate Mode Symbol Min (Note 1) unweighted TBD A-Weighted TBD unweighted - A-Weighted - (Note 1) THD - - - - kHz) - (Note 1) unweighted TBD A-Weighted TBD unweighted - A-Weighted - (Note 1) THD - - - - kHz) - CS43L42 High-Rate Mode Typ Max Min Typ Max 93 - TBD TBD -85 TBD - -85 TBD - -73 - -33 - -83 - -71 - -31 100 - - 100 90 - ...
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... Max TBD TBD - 0.5 x VA_LINE TBD 0. TBD - 0.5 x VA_HP - 0.1 - 100 - 0 High-Rate Mode Typ Max Min Typ - .4535 - - - - .4998 +. .577 - - - ±1.39/ ±0.23/Fs - +.2/-.1 - +.05/-.14 (Note 7) - +0/-.22 CS43L42 Units Vpp - VDC Vpp - VDC - dB - ppm/° Max Unit - Fs .4426 Fs .4984 Fs +0. ...
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... VL=1 D_L VA=3 VA_HP=3 A_HP VA_LINE=3 A_LINE VL=3 D_L VA=3 VA_HP=3 A_HP VA_LINE=3 A_LINE VL=3 D_L All Supplies=1.8 V All Supplies=3.0 V VA=1.8 V VA=3.0 V θ kHz) PSRR (60 Hz) CS43L42 Min Typ Max Units - µA - TBD - µA - TBD - µA - TBD - µA - TBD - µ ...
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... Symbol VA VA_HP VA_LINE IND stg (GND = 0V; all voltages with respect to ground.) Symbol (Note 10) VA_HP VA_LINE VL is limited by the Full-Scale Output Voltage V MIN . However, if distortion is not a concern, VA_HP may be FS_HP CS43L42 Typ Max Units - - µA - ± TBD - ...
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... MCLK/LRCK = 1024 MCLK/LRCK = 768 MCLK/LRCK = 768 MCLK/LRCK = 512 MCLK/LRCK = 512 t sclkl t sclkh Base Rate Mode t sclkw High Rate Mode t sclkw t slrd t slrs t sdlrs t sdh (Note 12) t sclkw t sclkr t sdlrs Base Rate Mode t sdh High Rate Mode t sdh CS43L42 Min Typ Max 100 ...
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... slrs t slrd lrs Figure 1. External Serial Mode Input Timing * The SCLK pulses shown are internal to the CS43L42. DS481PP2 sclkh t sclkl Figure 2. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS43L42 Figure 3. Internal Serial Clock Generation N equals MCLK divided by SCLK ...
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... Data must be held for sufficient time to bridge the transition time irs S top buf Symbol hdst t t high t sust (Note 14 susp 2 C protocol high hdst sud hdd Figure 4. Control Port Timing - Two-Wire Mode CS43L42 = 30 pF) L Min Max - 100 scl 500 - irs 4.7 - buf 4.0 - 4.7 - low 4 hdd 250 - sud ...
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... Figure 5. Control Port Timing - SPI Mode CS43L42 = 30 pF) L Min Max - 6 500 - 500 - 1 100 - 100 = 0 at all other times. spi t csh Unit MHz ns ns µ ...
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... LRCK 5 AOUTA SCLK/DEM1 3 SDATA AOUTB MUTEC CP/SA 1 RST VQ_HP 9 SDA/CDIN/DIF0 8 VQ_LINE SCL/CCLK/DIF1 4 AD0/CS/DEM0 FILT+ REF_GND GND 17 Figure 6. Typical Connection Diagram CS43L42 *Ferrite bead 0.9 to 3.3 V Supply + * 1.0 µF 220 µ 4.7 µH Ω 1k Headphones 220 µ 4.7 µH Ω 1k 560 Ω ...
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... BB2 BB1 BB0 BBCF0 TBCF1 TBCF0 ARATE6 ARATE5 ARATE4 ARATE3 RRATE6 RRATE5 RRATE4 RRATE3 TC0 TC_EN LIM_EN LINE1 LINE0 Reserved Reserved CS43L42 PDNHP PDNLN PDN Reserved HVOLA2 HVOLA1 HVOLA0 HVOLB2 HVOLB1 HVOLB0 DVOLA2 DVOLA1 DVOLA0 DVOLB2 DVOLB1 DVOLB0 TB3 TB2 ...
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... The zero cross function is independently monitored and implemented for each channel. Note: Ramped Digital and Analog is not available in High-Rate Mode SZC0 POR PDNHP CS43L42 PDNLN PDN RESERVED DS481PP2 ...
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... Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. DS481PP2 CS43L42 17 ...
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... The digital volume control affects both the line outputs and the headphone outputs. Setting this register to values greater than +18 dB will cause distortion in the audio outputs HVOLx4 HVOLx3 Decimal Value Volume Setting -10 -10 dB -15 - DVOLx4 DVOLx3 CS43L42 HVOLx2 HVOLx1 HVOLx0 DVOLx2 DVOLx1 DVOLx0 DS481PP2 ...
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... Treble Boost is not available in High-Rate Mode. Binary Code 0000 0010 1010 1001 1100 Table 4. Example Treble Boost Settings DS481PP2 Decimal Value Volume Setting 12 + -60 -60 dB -90 - BB1 BB0 TB3 Decimal Value Boost Setting +12 dB Decimal Value Boost Setting +12 dB CS43L42 TB2 TB1 TB0 ...
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... The AOUTA/HP_A and AOUTB/HP_B volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA/HP_A and AOUTB/HP_B are determined by the A Channel Attenuation and Volume Control Bytes, and the B Chan- nel Bytes are ignored when this function is enabled TBCF0 A CS43L42 DEM1 DEM0 VCBYP DS481PP2 ...
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... Use the LIM_EN bit to disable the limiter function (see Peak Signal Limiter Enable (LIM_EN)). Binary Code 00000001 00010100 00101000 00111100 01011010 Table 5. Example Limiter Attack Rate Settings DS481PP2 ARATE4 ARATE3 Decimal Value LRCK’s per 1 1.6 40 0.8 60 0.53 90 0.356 CS43L42 ARATE2 ARATE1 ARATE0 ...
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... TONE CONTROL ENABLE (TC_EN) Default = Disabled 1 - Enabled Function: The Bass Boost and Treble Boost features are active when this function is enabled RRATE4 RRATE3 Decimal Value LRCK’s per 1 512 LIM_EN ATAPI3 CS43L42 2 1 RRATE2 RRATE1 ATAPI2 ATAPI1 RRATE0 0 0 ATAPI0 1 DS481PP2 ...
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... Enabled Function: The CS43L42 will limit the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate register ...
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... Interface Format and the options are detailed in Figures 19-25. Note: Internal SCLK is not available when MCLKDIV is enabled LINE0 RESERVED RESERVED with VA = 1.8 VDC and VA_LINE = 3.0 VDC, then the gain factor would 24-bit data Internal SLCK) CS43L42 DIF2 DIF1 DIF0 DS481PP2 ...
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... DS481PP2 DIF0 DESCRIPTION 24-bit data Internal SLCK 24-bit data Internal SLCK Left Justified 24-bit data Right Justified, 24-bit data 0 Right Justified, 20-bit data 1 Right Justified, 16-bit data 0 Right Justified, 18-bit data 1 Identical to Format 1 Table 8. Digital Interface Format CS43L42 Format FIGURE ...
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... Operation in this mode is identical to operation with an external serial clock synchro- nized with LRCK. External Serial Clock Mode - The CS43L42 will enter the External Serial Clock Mode when- ever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period ...
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... Serial Control Interface Clock (Input) - Clocks the serial control data into or out of SDA/CDIN. Serial Control Data I/O (Input/Output Two-Wire mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. CS43L42 External SCLK DEMO DESCRIPTION ...
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... No Connection - This pin has no internal connection to the device. Mode Select (Input) - The Mode Select pin is used to select control port or stand-alone mode. When high, the CS43L42 will operate in control port mode. When low, the CS43L42 will operate in stand-alone mode. Headphone Quiescent Voltage (Output) - Filter connection for internal headphone amp quiescent reference voltage ...
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... Clock Modes The CS43L42 operates in one of two clocking modes. Base Rate Mode supports input sample rates kHz, and High Rate Mode supports input sample rates up to 100 kHz, see Table 10 and 11 ...
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... The control port has 2 modes: SPI and Two-Wire, with the CS43L42 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied GND. If the CS43L42 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. 7.1 SPI Mode ...
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... tio rite , yte DS481PP2 Reserved MAP3 ADDRESS MSB R/W byte ory A d dres s P oin te r Figure 7. Control Port Timing, SPI mode N ote Figure 8. Control Port Timing, Two-Wire Mode CS43L42 2 1 MAP2 MAP1 0 0 DATA byte 1-8 Stop 0 MAP0 0 31 ...
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... Figure 13. High-Rate Stopband Rejection 32 Figure 10. Base-Rate Transition Band Figure 12. Base-Rate Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.6 0.7 0.8 0.9 1.0 0.40 CS43L42 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 Frequency (normalized to Fs) Figure 14. High-Rate Transition Band 0.58 0.60 DS481PP2 ...
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... AOUTx R L AGND Figure 17. Line Output Test Load 220 µF + HP_x R L AGND Figure 18. Headphone Output Test Load CS43L42 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Frequency (normalized to Fs) Figure 16. High-Rate Passband Ripple V out out C L ...
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... Figure 20. CS43L42 Control Port Mode - Serial Audio Format 1 Left Internal SCLK Mode Left Justified 24-Bit Data INT SCLK = MCLK/LRCK = 512, 256 or 128 INT SCLK = MCLK/LRCK = 384 or 192 Figure 21. CS43L42 Control Port Mode - Serial Audio Format LSB MSB - 24-Bit Data Data Valid on Rising Edge of SCLK + LSB MSB - ...
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... Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4 LRCK SCLK SDATA cks Internal SCLK Mode Right Justified, 16-Bit Data INT SCLK = MCLK/LRCK = 512, 256 or 128 INT SCLK = MCLK/LRCK = 384 or 192 Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5 DS481PP2 Right Justified, 24-Bit Data ...
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... 24-Bit data and INT SCLK = MCLK/LRCK = 384 or 192 Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0 Left Internal SCLK Mode Left Justified 24-Bit Data INT SCLK = MCLK/LRCK = 512, 256 or 128 INT SCLK = MCLK/LRCK = 384 or 192 Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format ...
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... SCLK SDATA cks Internal SCLK Mode Right Justified, 24-Bit Data INT SCLK = MCLK/LRCK = 512, 256 or 128 INT SCLK = MCLK/LRCK = 384 or 192 Figure 28. CS43L42 Stand Alone Mode - Serial Audio Format 2 LRCK SCLK SDATA cks Internal SCLK Mode Right Justified, 16-Bit Data INT SCLK = MCLK/LRCK = 512, 256 or 128 INT SCLK = MCLK/LRCK = 384 or 192 Figure 29 ...
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... Gain dB 0dB -10dB Left Channel Audio Data Right Channel Audio Data 38 T1=50 µ µ Frequency 3.183 kHz 10.61 kHz Figure 30. De-Emphasis Curve A Channel Digital EQ Volume Control Σ B Channel Digital EQ Volume Control Figure 31. ATAPI Block Diagram CS43L42 MUTE AoutA/HP_A MUTE AoutB/HP_B DS481PP2 ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB43L42 Evaluation Board Datasheet 2 3) “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com DS481PP2 CS43L42 39 ...
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... JEDEC #: MO-153 Controlling Dimension is Millimeters. CS43L42 END VIEW L MILLIMETERS NOM MAX -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 7.80 7.90 6.40 6.50 4.40 4.50 0.65 BSC -- 0 ...