AD9709ASTZ Analog Devices Inc, AD9709ASTZ Datasheet - Page 16

• Manufacturer Part Number: AD9709ASTZ
• Description: IC DAC 8BIT DUAL 125MSPS 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9709ASTZ

• Data Interface: Parallel
• Settling Time: 35ns
• Number Of Bits: 8
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 450mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 8bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 3V To 5.5V
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9709-EBZ - BOARD EVAL FOR AD9709
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9709
Timing specifications for interleaved mode are shown in Figure 28
and Figure 30.
The digital inputs are CMOS compatible with logic thresholds,
V
(DVDDx) or
At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 29, but at 3.3 V the interleaved data transfer is
not reliable.
THRESHOLD
DATA IN
DATA IN
V
IQWRT
IQWRT
IQCLK
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
IQCLK
IQSEL
IQSEL
I
I
I
I
THRESHOLD
OUTA
OUTB
OUTA
OUTB
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
OR
OR
, set to approximately half the digital positive supply
Figure 28. 5 V or 3.3 V Interleaved Mode Timing
Figure 29. 5 V Only Interleaved Mode Timing
= DVDDx/2 (±20%)
t
t
H
H
*
*
500 ps
t
t
S
S
t
PD
t
PD
500 ps
t
t
H
H
t
t
LPW
LPW
Rev. B | Page 16 of 32
The internal digital circuitry of the AD9709 is capable of operating
at a digital supply of 3.3 V or 5 V. As a result, the digital inputs
can also accommodate TTL levels when DVDD1/DVDD2 is set to
accommodate the maximum high level voltage (V
TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper
compatibility with most TTL logic families. Figure 31 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it
contains an active pull-down circuit, thus ensuring that the
AD9709 remains enabled if this input is left disconnected.
Because the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD1/DVDD2) results in the lowest data feedthrough and
on-chip digital noise. The drivers of the digital data interface
circuitry should be specified to meet the minimum setup and
hold times of the AD9709 as well as its required minimum and
maximum input logic level thresholds.
INTERLEAVED
DAC OUTPUT
DAC OUTPUT
IQRESET
PORT 1
PORT 2
IQWRT
IQCLK
IQSEL
DATA
DIGITAL
xx
Figure 30. Interleaved Mode Timing
INPUT
Figure 31. Equivalent Digital Input
D1
xx
xx
D2
D3
DVDD1
D1
D2
D4
OH(MAX)
D5
D3
D4
) of the