SLCF2GM2PUI STEC, SLCF2GM2PUI Datasheet - Page 8

• Manufacturer Part Number: SLCF2GM2PUI
• Manufacturer: STEC
• Type: CompactFlashr

Specifications of SLCF2GM2PUI

• Density: 2GByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: Not Required
• Pin Count: 50
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.97/4.5V
• Operating Supply Voltage (max): 3.63/5.5V
• Programmable: Yes
• Lead Free Status / Rohs Status: Compliant

SLCFxxx(G)M2PU(I)
Datasheet
–HDMARDY
(All Modes: UDMA protocol
DMA Read)
HSTROBE
(All Modes: UDMA protocol
DMA Write)
-IORD
(PC Card I/O Mode except
UDMA protocol active)
-HDMARDY
(All Modes: UDMA protocol
DMA Read)
HSTROBE
(All Modes: UDMA protocol
DMA Write)
-IORD
(True IDE Mode except
UDMA protocol active)
-HDMARDY
(All Modes: UDMA protocol
DMA Read)
HSTROBE
(All Modes: UDMA protocol
DMA Write)
-WE
(PC Card Memory Mode)
-WE
(PC Card I/O Mode)
-WE
(True IDE Mode)
-OE
(PC Card Memory Mode)
-OE
(PC Card I/O Mode)
-ATASEL
(True IDE Mode)
RDY/-BSY
(PC Card Memory Mode)
-IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
I
I
O
36
9
37
61000-05610-108, April 2009
In all modes when UDMA mode DMA Read is active, this
signal is asserted by the host to indicate that the host is
ready to receive UDMA data-in bursts. The host may negate
-HDMARDY to pause an UDMA transfer
In all modes when UDMA mode DMA Write is active, this
signal is the data out strobe generated by the host. Both the
rising and falling edge of HSTROBE cause data to be latched
by the device. The host may stop generating HSTROBE
edges to pause an UDMA data-out burst.
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto the bus from the CF Card.
Same as –HDMARDY above.
Same as HSTROBE above.
In True IDE Mode, this signal has the same function as in PC
Card I/O Mode.
Same as –HDMARDY above.
Same as HSTROBE above.
This is a signal driven by the host and used for strobing
memory write data into the registers. It is also used for writing
the configuration registers.
In PC Card I/O Mode, this signal is used for writing the
configuration registers.
In True IDE Mode, this input signal is not used and should be
connected to VCC.
This is an Output Enable strobe generated by the host
interface. It is used to read data from the CF Card in PC Card
Memory Mode and to read the CIS and configuration
registers.
In PC Card I/O Mode, this signal is used to read the CIS and
configuration registers.
To enable True IDE Mode, this input should be grounded by
the host.
In Memory Mode, this signal is set high when the CF Card is
ready to accept a new data transfer operation and held low
when the CF Card is busy. The host must provide a pull-up
resistor. At power up and at reset, the RDY/-BSY signal is
held low (busy) until the CF Card completes its power up or
reset function. No access of any type should be made to the
CF Card during this time. The RDY/-BSY signal is held high
(disabled from being busy) when the CF Card is powered up
with RESET continuously disconnected or asserted high.
After card has been configured for I/O operation, signal is
used as active low interrupt request. Strobe low to generate
pulse mode interrupt or hold low for level mode interrupt.
In True IDE Mode, this signal is the active high interrupt
request to the host.
CompactFlash Card
8