EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 15

• Manufacturer Part Number: EMC6D102-CZC-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of EMC6D102-CZC-TR

• Operating Current: 3mA
• Operating Temperature Classification: Commercial
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
4.4
4.4.1
4.5
Bits:
FIELD
FIELD:
Bits
START
START
Invalid Protocol Response Behavior
General Call Address Response
Write Byte
The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol
shown in
Read Byte
The Read Byte protocol is used to read data from the registers. The data will only be read if the
protocol shown in
protocol.
Registers that are accessed with an invalid protocol will not be updated. A register will only be updated
following a valid protocol. The only valid protocols are the Write Byte and Read Byte protocols, which
are described above.
The EMC6D102 device responds to three SMBus slave addresses:
1. The SMBus slave address that supports the valid protocols defined in the previous sections is
2. SMBus Alert Response (0001 100). The SMBus will only respond to the SMBus Alert Response
Attempting to communicate with the Hardware Monitor Block over SMBus with an invalid slave
address, or invalid protocol will result in no response, and the SMBus Slave Interface will return to the
idle state.
The only valid registers that are accessible by the SMBus slave address are the registers defined in
the Registers Section. See
Undefined Registers
Reads to undefined registers return 00h. Writes to undefined registers have no effect and return no
error.
The EMC6D102 will not respond to a general call address of 0000_000.
1
1
determined by the level on the Address Select and Address Enable pins as shown in
"Slave Address," on page
Address if the SMBus Alert Response interrupt was generated to request a response from the Host.
The SMBus Alert Response is defined in
page
SLAVE
ADDR
SLAVE ADDR
7
16.
Table 4.2
7
WR
1
Table 4.3
is performed correctly. Only one byte is transferred at time for a Write Byte protocol.
ACK
1
Table 4.2 SMBus Write Byte Protocol
Table 4.3 SMBus Read Byte Protocol
WR
Section 4.4.1, "Undefined Registers"
is performed correctly. Only one byte is transferred at time for a Read Byte
1
ADDR
REG.
13.
8
ACK
DATASHEET
1
ACK
1
15
REG. ADDR
START
1
Section 4.10, "SMBus Alert Response Address," on
8
SLAVE
ADDR
7
ACK
1
RD
1
for response to undefined registers.
REG. DATA
ACK
1
8
DATA
REG.
8
Revision 0.4 (09-25-07)
ACK
NACK
1
1
Section 4.1,
STOP
STOP
1
1