DS4432U+ Maxim Integrated Products, DS4432U+ Datasheet - Page 7

• Manufacturer Part Number: DS4432U+
• Description: IC DAC 7BIT 2CH 5.5V 8-MSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS4432U+

• Number Of Bits: 7
• Data Interface: I²C, Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Number Of Dac Outputs: 2
• Resolution: 7 bit
• Interface Type: I2C
• Settling Time: 1.3 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 150 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 1. I
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 1 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 1 for
applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup and hold time requirements (Figure 1).
STOP
2
C Timing Diagram
t
BUF
START
_______________________________________________________________________________________
t
HD:STA
IL(MAX)
t
LOW
AND V
Dual-Channel, I
IH(MIN)
t
R
.
t
HD:DAT
t
HIGH
t
F
t
SU:DAT
REPEATED
Data is shifted into the device during the rising edge
of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 1) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses, including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a one during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 2). An
ACK is the acknowledgement that the device is
properly receiving data. A NACK is used to termi-
nate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit-write definition,
and the acknowledgement is read using the bit-read
definition.
START
2
C, 7-Bit Sink/Source
t
SU:STA
t
HD:STA
Current DAC
t
SP
t
SU:STO
7