CY7C4282-10ASC Cypress Semiconductor Corp, CY7C4282-10ASC Datasheet - Page 4

• Manufacturer Part Number: CY7C4282-10ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282-10ASC

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06009 Rev. *B
Programming
When LD is held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, LD
can be used to access the four 9-bit offset registers contained
in the CY7C4282/CY7C4292 for writing or reading data to
these registers.
When the device is configured for programmable flags and
both LD and WEN are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and
fourth LOW-to-HIGH transitions of WCLK store data in the
empty offset most significant bit (MSB) register, full offset LSB
register, and full offset MSB register, respectively, when LD
and WEN are LOW. The fifth LOW-to-HIGH transition of
WCLK while LD and WEN are LOW writes data to the empty
LSB register again. Figure 1 shows the registers sizes and
default values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the LD input HIGH, the FIFO is returned to normal read and
write operation. The next time LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when LD is LOW and REN is LOW. LOW-to-HIGH
transitions of RCLK read register contents to the data outputs.
Writes and reads should not be performed simultaneously on
the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
Note:
1.
8
8
8
8
Figure 1. Offset Register Location and Default Values
The same selection sequence applies to reading from the registers. REN is enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
7
7
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
64K × 9
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
0
0
0
0
8
8
8
8
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
128K × 9
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
0
0
0
0
sponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAE is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAF is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4282 (64K – m) and
CY7C4292 (128K – m). PAF is set HIGH by the LOW-to-HIGH
transition of WCLK when the number of available memory
locations is greater than m.
Flag Operation
The CY7C4282/CY7C4292 devices provide four flag pins to
indicate the condition of the FIFO contents. All flags operate
synchronously.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclu-
sively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
LD
0
0
1
1
WEN
0
1
0
1
WCLK
[1]
No Operation
Write Into FIFO
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Selection
CY7C4282
CY7C4292
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