CY7C4282-10ASC Cypress Semiconductor Corp, CY7C4282-10ASC Datasheet - Page 7

• Manufacturer Part Number: CY7C4282-10ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282-10ASC

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06009 Rev. *B
Depth Expansion Configuration
The CY7C4282/92 can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282/92s. Maximum
depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
4. EF and FF composite flags are created by O-Ring together
DATAIN (D)
Load (FL) control input.
the Expansion In (XI) pin of the next device.
each individual respective flag.
FF
Figure 3. Block Diagram of 64Kx9/128Kx9 One Meg Deep Sync FIFO Memory
WRITECLOCK (WCLK)
WRITEENABLE (WEN)
RESET (RS)
with Programmable Flags used in Depth Expansion Configuration
FIRST LOAD (FL)
V
V
CC
CC
D
D
WEN
WCLK
WEN
RS
WCLK
RS
D
WCLK
WEN
RS
FF
FL
FF
FF
FL
FL
7C4282
7C4292
7C4282
7C4292
7C4282
7C4292
XO
XO
XO
XI
XI
XI
RCLK
RCLK
RCLK
REN
REN
OE
REN
OE
OE
EF
EF
EF
Q
Q
Q
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUTENABLE (OE)
EF
DATA OUT (Q)
CY7C4282
CY7C4292
Page 7 of 16
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