MT48H16M32LFCM-8 IT:A TR Micron Technology Inc, MT48H16M32LFCM-8 IT:A TR Datasheet - Page 52

• Manufacturer Part Number: MT48H16M32LFCM-8 IT:A TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M32LFCM-8 IT:A TR

• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 9/7ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
23. The only time that the clock frequency is allowed to change is during clock stop,
24. Auto precharge mode only. The precharge timing budget (
25. Parameter guaranteed by design.
26. CKE is HIGH during refresh command period
27. Values for I
28. I
29. Current is taken 500ms after entering into this operating mode to allow tester mea-
30. Deep power-down current is a nominal value at 25°C. This parameter is not tested.
31. There must be one
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
cannot be greater than one third of the cycle rate. V
a pulse width ≤ 3ns.
power down, or self-refresh modes.
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.
limit is actually a nominal value and does not result in a fail value.
sampled only.
suring unit settling time.
DD
OUT
IH
specifications are tested after the device is properly initialized.
overshoot: V
DD
= 4mA for full-drive strength. Other drive strengths require appropriate scale.
current will increase or decrease proportionally according to the amount of
t
CK = 7.5ns for -75, and
DD
7 for 85°C are 100 percent tested. Values for 70°C, 45°C, and 15°C are
IH
(MAX) = V
t
CK during the
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
IH
or V
52
t
t
t
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
DD
IL
Q + 2V for a pulse width ≤ 3ns, and the pulse width
levels.
t
CK = 8ns for -8, CL = 3.
t
WR time for WRITE auto precharge.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP; clock(s) specified as a reference only at
t
RFC (MIN), else CKE is LOW. The I
IL
undershoot: V
t
RP) begins at 7ns for -8
©2005 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
Notes
DD
7