N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet
N25Q128A11B1240E
Specifications of N25Q128A11B1240E
Related parts for N25Q128A11B1240E
N25Q128A11B1240E Summary of contents
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... Additional 2 Extended Device ID (EDID) bytes to identify device factory options – Unique ID code (UID) with 14 bytes read- only, available upon customer request 100,000 + program/erase cycles per sector More than 20 years data retention Packages – RoHS compliant Rev 1.0 N25Q128 SO16 (SF) 300 mils width 1/185 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 ...
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Quad Input Command VECR<7> 6.4.2 Dual Input Command VECR<6> ...
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Program OTP instruction (POTP 9.1.17 Subsector Erase (SSE) . ...
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Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ...
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XIP Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 49. Dual Command Page Program instruction sequence DSP, 02h . . . . . . . . . . . . . . . . . . . 118 Figure 50. Dual Command Page Program instruction sequence DSP, A2h ...
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Figure 101. Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection mechanisms accessed by a high speed SPI-compatible bus and features the possibility to work in XIP (“eXecute in Place”) mode. The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations ...
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... Many different N25Q128 configurations are available, please refer to the ordering scheme page for the possibilities. Additional features are available as security options (The Security features are described in a dedicated Application Note). Please contact your nearest Numonyx Sales office for more information. Figure 1. Logic diagram Note: Reset functionality is available in devices with a dedicated part number ...
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Note: There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to VSS, and must not be connected to any other voltage or signal line on the PCB. Figure 2. VDFPN8 connections 1. ...
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Figure 4. BGA connections Connect. 2. See Figure 116.: TBGA - mm, 24-ball, mechanical package ...
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Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as an Input ...
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Hold (HOLD) or Reset (Reset) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. Reset functionality is present instead of Hold in devices with a dedicated part number. See Section ...
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Write protect/enhanced program supply voltage (W/VPP), DQ2 W/VPP/DQ2 can be used as: A protection control input. A power supply pin. I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions. When the device is operated in Extended ...
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SPI Modes These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising ...
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SPI bus in high impedance. Example pF, that is R*C p master never leaves the SPI ...
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SPI Protocols The N25Q128 memory can work with 3 different Serial protocols: Extended SPI protocol. Dual I/O SPI (DIO-SPI) protocol. Quad I/O SPI (QIO-SPI) protocol possible to choose among the three protocols by means of user volatile ...
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Quad SPI (QIO-SPI) protocol Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3). The exception is the Program/Erase cycle performed with the VPP, in which ...
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Operating features 5.1 Extended SPI Protocol Operating features 5.1.1 Read Operations To read the memory content in Extended SPI protocol different instructions are available: READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad Output Fast ...
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Quad Input Fast Program The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256 bytes using 4 input pins at the same time (by changing bits from 1 to 0). For optimized timings, it ...
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When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The ...
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Table 2. Device Status after Reset Low Pulse Conditions: reset pulse occurred (1) While decoding an instruction : WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, DOFR, DIOFR, QOFR, QIOFR, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP Under completion ...
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Dual SPI (DIO-SPI) Protocol In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are transmitted on two data lines. All the functionality available in the Extended SPI protocol is also available in the DIO-SPI protocol. ...
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The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte two instructions are required: Write Enable (WREN), which is one byte, and a Dual Command Page Program (DCPP) sequence, which consists of four bytes ...
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Quad SPI (QIO-SPI)Protocol In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are transmitted on four data lines, with the exception of the polling instructions performed during a Program or Erase cycle performed with VPP, ...
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This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided ...
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Read and Modify registers The read and modify register instructions are available and behave in QIO-SPI protocol exactly as they do in Extended SPI protocol, the only difference is that instruction codes, addresses and output data are transmitted across ...
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Volatile and Non Volatile Registers The device features many different registers to store, in volatile or non volatile mode, many parameters and operating configurations: Legacy SPI Status Register 3 configuration registers: – Non Volatile Configuration Register (NVCR), 16 bits ...
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... Each register can be read and modified by means of dedicated instructions in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Reading time for all registers is comparable; writing time instead is very different: NVCR bits are set as Flash Cell memory content requiring a longer time to perform internal writing cycles. See Table 33.: AC Characteristics ...
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Legacy SPI Status Register The Status Register contains a number of status and control bits that can be read or set by specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This is available in all the ...
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The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array: ...
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Table 4. Non-Volatile Configuration Register Bit Parameter 0000 0001 0010 0011 0100 0101 0110 0111 1000 Dummy clock NVCR<15:12> 1001 cycle 1010 1011 1100 1101 1110 1111 000 001 010 011 XIP enabling NVCR<11:9> at POR 100 101 110 111 ...
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Table 4. Non-Volatile Configuration Register Bit Parameter 111 0 Fast POR x NVCR<5> READ 1 0 Reset/Hold NVCR<4> disable 1 0 Quad Input NVCR<3> Command 1 0 Dual Input NVCR<2> Command 1 NVCR<1:0> Reserved xx 6.2.1 Dummy clock cycle NV ...
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XIP NV configuration bits (NVCR bits from The bits from the Non Volatile Configuration register store the default settings for the XIP operation, allowing the memory to start working directly on the ...
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Dual Input NV configuration bit (NVCR bit 2) The Dual Input NV configuration bit can be used to make the memory start working in DIO- SPI protocol directly after the power on sequence. The products are delivered with this ...
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Table 6. Volatile Configuration Register Bit Parameter 0000 0001 0010 0011 0100 0101 0110 0111 1000 Dummy clock VCR<7:4> 1001 cycle 1010 1011 1100 1101 1110 1111 0 VCR<3> XIP 1 VCR<2:0> Reserved xxx 6.3.1 Dummy clock cycle Volatile Configurations ...
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XIP Volatile Configuration bits (VCR bit 3) The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set enable the memory working on XIP mode. For devices with a ...
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Table 7. Volatile Enhanced Configuration Register Bit Parameter VECR<7> Quad Input Command VECR<6> Dual Input Command VECR<5> Reserved VECR<4> Reset/Hold disable Accelerator pin enable in VECR<3> QIO-SPI protocol or in QIFP/QIEFP VECR<2:0> Output Driver Strength 6.4.1 Quad Input Command VECR<7> ...
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Reset/Hold disable VECR<4> The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register (WVECR) instruction. This feature can be useful ...
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Flag Status Register The Flag Status Register is a powerful tool to investigate the status of the device, checking information regarding what is actually doing the memory and detecting possible error conditions. The Flag status register is composed by ...
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Table 8. Flag Status Register BIT 7 P/E Controller (not WIP) 6 Erase Suspend 5 Erase 4 Program 3 VPP 2 Program Suspend 1 Protection 0 RESERVED 6.5.1 P/E Controller Status bit The bit 7 of the Flag Status register ...
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The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI). Once the bit 5 is set High, it can only be ...
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The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command (PES) has been issued, therefore the device may still complete the operation before entering the Suspend Mode. The Program Suspend ...
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Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 7.1 SPI Protocol-related protections This applies to all three protocols. The environments where non-volatile memory devices are used can be very noisy. No ...
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The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock bit and the Lock ...
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Table 10. Protected area sizes (TB bit = 0) Status Register Content TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit ...
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Table 11. Protected area sizes (TB bit = 1) Status Register Content TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit ...
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Memory organization The memory is organized as: 16,777,216 bytes (8 bits each) 256 sectors (64 Kbytes each) In Bottom and Top versions: 8 bottom (top) 64 Kbytes boot sectors with 16 subsectors (4 Kbytes) and 248 standard 64 KB ...
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Table 12. Memory organization (uniform) (page Sector Address range 255 FF0000 FFFFFF 254 FE0000 FEFFFF 253 FD0000 FDFFFF 252 FC0000 FCFFFF 251 FB0000 FBFFFF 250 FA0000 FAFFFF 249 F90000 F9FFFF 248 F80000 F8FFFF 247 F70000 F7FFFF 246 ...
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Table 12. Memory organization (uniform) (page Sector 221 DD0000 220 DC0000 219 DB0000 218 DA0000 217 D90000 216 D80000 215 D70000 214 D60000 213 D50000 212 D40000 211 D30000 210 D20000 209 D10000 208 D00000 207 CF0000 ...
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Table 12. Memory organization (uniform) (page Sector Address range 186 BA0000 BAFFFF 185 B90000 B9FFFF 184 B80000 B8FFFF 183 B70000 B7FFFF 182 B60000 B6FFFF 181 B50000 B5FFFF 180 B40000 B4FFFF 179 B30000 B3FFFF 178 B20000 B2FFFF 177 ...
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Table 12. Memory organization (uniform) (page Sector 151 970000 150 960000 149 950000 148 940000 147 930000 146 920000 145 910000 144 900000 143 8F0000 142 8E0000 141 8D0000 140 8C0000 139 8B0000 138 8A0000 137 890000 ...
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Table 12. Memory organization (uniform) (page Sector Address range 116 740000 74FFFF 115 730000 73FFFF 114 720000 72FFFF 113 710000 71FFFF 112 700000 70FFFF 111 6F0000 6FFFFF 110 6E0000 6EFFFF 109 6D0000 6DFFFF 108 6C0000 6CFFFF 107 ...
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Table 12. Memory organization (uniform) (page Sector 81 510000 80 500000 79 4F0000 78 4E0000 77 4D0000 76 4C0000 75 4B0000 74 4A0000 73 490000 72 480000 71 470000 70 460000 69 450000 68 440000 67 430000 ...
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Table 12. Memory organization (uniform) (page Sector Address range 46 2E0000 2EFFFF 45 2D0000 2DFFFF 44 2C0000 2CFFFF 43 2B0000 2BFFFF 42 2A0000 2AFFFF 41 290000 29FFFF 40 280000 28FFFF 39 270000 27FFFF 38 260000 26FFFF 37 ...
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Table 12. Memory organization (uniform) (page Sector 11 B0000 10 A0000 9 90000 8 80000 7 70000 6 60000 5 50000 4 40000 3 30000 2 20000 1 10000 0 0 Table 13. Memory organization (bottom) (page ...
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Table 13. Memory organization (bottom) (page Sector Subsector 235 - EB0000 234 - EA0000 233 - E90000 232 - E80000 231 - E70000 230 - E60000 229 - E50000 228 - E40000 227 - E30000 226 - ...
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Table 13. Memory organization (bottom) (page Sector Subsector 200 - 199 - 198 - 197 - 196 - 195 - 194 - 193 - 192 - 191 - 190 - 189 - 188 - 187 - 186 ...
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Table 13. Memory organization (bottom) (page Sector Subsector 165 - A50000 164 - A40000 163 - A30000 162 - A20000 161 - A10000 160 - A00000 159 - 9F0000 158 - 9E0000 157 - 9D0000 156 - ...
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Table 13. Memory organization (bottom) (page Sector Subsector 130 - 129 - 128 - 127 - 126 - 125 - 124 - 123 - 122 - 121 - 120 - 119 - 118 - 117 - 116 ...
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Table 13. Memory organization (bottom) (page Sector Subsector 95 - 5F0000 94 - 5E0000 93 - 5D0000 92 - 5C0000 91 - 5B0000 90 - 5A0000 89 - 590000 88 - 580000 87 - 570000 86 - ...
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Table 13. Memory organization (bottom) (page Sector Subsector ...
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Table 13. Memory organization (bottom) (page Sector Subsector 25 - 190000 24 - 180000 23 - 170000 22 - 160000 21 - 150000 20 - 140000 19 - 130000 18 - 120000 17 - 110000 16 - ...
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Table 13. Memory organization (bottom) (page Sector Subsector Table 14. Memory organization (top) Sector Subsector 127 255 112 111 254 96 95 253 80 79 252 64 63 251 48 47 ...
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Table 14. Memory organization (top) Sector Subsector 244 - F40000 243 - F30000 242 - F20000 241 - F10000 240 - F00000 239 - EF0000 238 - EE0000 237 - ED0000 236 - EC0000 235 - EB0000 234 - EA0000 ...
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Table 14. Memory organization (top) Sector Subsector 209 - 208 - 207 - 206 - 205 - 204 - 203 - 202 - 201 - 200 - 199 - 198 - 197 - 196 - 195 - 194 - 193 ...
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Table 14. Memory organization (top) Sector Subsector 174 - AE0000 173 - AD0000 172 - AC0000 171 - AB0000 170 - AA0000 169 - A90000 168 - A80000 167 - A70000 166 - A60000 165 - A50000 164 - A40000 ...
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Table 14. Memory organization (top) Sector Subsector 139 - 138 - 137 - 136 - 135 - 134 - 133 - 132 - 131 - 130 - 129 - 128 - 127 - 126 - 125 - 124 - 123 ...
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Table 14. Memory organization (top) Sector Subsector 104 - 680000 103 - 670000 102 - 660000 101 - 650000 100 - 640000 99 - 630000 98 - 620000 97 - 610000 96 - 600000 95 - 5F0000 94 - 5E0000 ...
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Table 14. Memory organization (top) Sector Subsector ...
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Table 14. Memory organization (top) Sector Subsector 34 - 220000 33 - 210000 32 - 200000 31 - 1F0000 30 - 1E0000 29 - 1D0000 28 - 1C0000 27 - 1B0000 26 - 1A0000 25 - 190000 24 - 180000 ...
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Instructions The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI. Each protocol has a dedicated instruction set, and each instruction set features the same functionality: Read, program and erase the memory and the 64 byte ...
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In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE), Bulk ...
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Table 15. Instruction set: extended SPI protocol (page Instruction Description RDID Read Identification READ Read Data Bytes FAST_READ Read Data Bytes at Higher Speed DOFR Dual Output Fast Read DIOFR Dual Input/Output Fast Read QOFR Quad Output ...
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Table 15. Instruction set: extended SPI protocol (page Instruction Description Read Volatile Enhanced RDVECR Configuration Register Write Volatile Enhanced WRVECR Configuration Register DP Deep Power-down RDP Release from Deep Power-down 1) The Number of dummy clock cycles ...
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Table 16. Read Identification data-out sequence Manufacturer Device identification Identification Memory type 20h BBh Table 17. Extended Device ID table (first byte) Bit 7 Bit 6 Bit 5 Reserved Reserved Reserved Figure 10. Read identification instruction and data-out sequence 9.1.2 ...
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Figure 11. Read Data Bytes instruction and data-out sequence Instruction DQ0 High Impedance DQ1 9.1.3 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. ...
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Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence Instruction DQ0 High Impedance DQ1 ...
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Figure 13. Dual Output Fast Read instruction sequence S Mode Mode 2 Instruction DQ0 DQ1 Dummy cycles DQ0 ...
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Figure 14. Dual I/O Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 DQ1 switches from ...
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Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering Figure 15. Quad Input/Output Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 ...
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Figure 16. Quad Input/ Output Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ 9.1.8 Read OTP (ROTP) The device is first selected by ...
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Figure 17. Read OTP instruction and data-out sequence Instruction DQ0 High Impedance DQ1 Dummy cycles 7 ...
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WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register): to verify if the POR sequence is completed is ...
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The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write lo Lock Register (WRLR) instruction completion Write Non Volatile Configuration Register (WRNVCR) instruction completion Write ...
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Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched ...
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Figure 20. Page Program instruction sequence Instruction DQ0 Data byte DQ0 MSB ...
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Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See Table 33.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the ...
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Dual Input Extended Fast Program The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input Fast Program (DIFP), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1) ...
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If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to ...
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Figure 24. Quad Input Extended Fast Program instruction sequence Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ 9.1.16 Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program ...
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Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'. Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the ...
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Figure 26. How to permanently lock the OTP bytes Byte Byte Byte 9.1.17 Subsector Erase (SSE) For devices with bottom or top architecture, at the bottom (or top) of the addressable area there are 8 boot sectors, ...
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Figure 27. Subsector Erase instruction sequence DQ0 9.1.18 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must ...
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Figure 28. Sector Erase instruction sequence S C DQ0 9.1.19 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After ...
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Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input Page Program, Dual Input Extended Page program, Quad Input Page Program and ...
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Table 19. Operations Allowed / Disallowed During Device States Device States and Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No) Standby State Program State Operation Sector Same Other Same All Reads except RDSR / Yes Yes RDFSR Array Program: PP ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. ...
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Figure 31. Write Status Register instruction sequence Instruction DQ0 High Impedance DQ1 The protection features of the device ...
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Table 20. Protection modes W / VPP SRWD Mode Signal bit 1 0 Status register is writeable, if the WREN instruction has set the WEL 0 0 Software bit. protected The values in the SRWD, TB, BP3, (SPM ...
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Table 21. Lock Register out Bit Bit name Value b7-b2 The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the ‘1’ Sector Lock Lock Down bit it cannot be cleared to ‘0’, except ...
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Table 22. Lock Register in Sector All sectors 1. Values of (b1, b0) after power-up are defined in 9.1.26 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. The Status ...
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Figure 35. Clear Flag Status Register instruction sequence S C DQ0 DQ1 9.1.28 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 36. Read NV Configuration Register ...
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As soon as Chip Select (S) is driven High, the self-timed write NV configuration register cycle (whose duration is tnvcr) is initiated. While the Write Non Volatile Configuration register cycle is in progress possible to monitor the end ...
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Figure 38. Read Volatile Configuration Register instruction sequence Instruction DQ0 High Impedance DQ1 9.1.31 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the ...
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Figure 39. Write Volatile Configuration Register instruction sequence DQ0 High Impedance DQ1 9.1.32 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 40. ...
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The Write Volatile Enhanced Configuration register (WRVECR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data input (DQ0). Chip Select (S) must be driven High after the eighth ...
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The Deep Power-down mode automatically stops at power-down, and the device always powers up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data ...
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Figure 43. Release from Deep Power-down instruction sequence Instruction DQ0 High Impedance DQ1 9.2 DIO-SPI Instructions In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on two wires: DQ0 and DQ1. In ...
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Table 23. Instruction set: DIO-SPI protocol Instruction Description MIORDID Multiple I/O read identification DCFR Dual Command Fast Read ROTP Read OTP WREN Write Enable WRDI Write Disable DCPP Dual Command Page Program POTP Program OTP (2) SSE SubSector Erase SE ...
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The number of Dummy Clock cycles is configurable by the user 1) SSE is only available in devices with Bottom or Top architecture. 2) 9.2.1 Multiple I/O Read Identification protocol The Multiple Input/Output Read Identification (MIORDID) instruction allows to read ...
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Dual Command Fast Read (DCFR) The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI protocol, parallelizing the instruction code, the address and the output data on two pins (DQ0 and DQ1). The Dual Command ...
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Figure 46. Read OTP instruction and data-out sequence DIO-SPI Instruction 24-Bit Address DQ0 DQ1 ...
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Figure 48. Write Disable instruction sequence DIO-SPI S C DQ0 DQ1 9.2.6 Dual Command Page Program (DCPP) The Dual Command Page Program (DCPP) instruction allows to program the memory content in DIO-SPI protocol, parallelizing the instruction code, the address and ...
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Figure 50. Dual Command Page Program instruction sequence DSP, A2h Instruction DQ0 DQ1 Figure 51. Dual Command Page Program instruction sequence DSP, D2h S ...
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Figure 52. Program OTP instruction sequence DIO-SPI Instruction DQ0 DQ1 9.2.8 Subsector Erase (SSE) For devices with bottom or top architecture, at the bottom (or ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the ...
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Figure 55. Bulk Erase instruction sequence DIO-SPI S C DQ0 DQ1 9.2.11 Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase and Dual Command Page Program can be ...
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Extended SPI protocol, please refer to Resume for further details. Figure 57. Program/Erase Resume instruction sequence DIO-SPI S C DQ0 DQ1 Section 9.1.21: Program/Erase Instruction Dual_Program_Erase_Resume 123/185 ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 and DQ1, the instruction functionality ...
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Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, the address and the output data on the two pins DQ0 and DQ1, the ...
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Figure 61. Write to Lock Register instruction sequence DIO-SPI Instruction DQ0 DQ1 9.2.17 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the ...
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Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits (Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit not necessary to set the WEL bit ...
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Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. ...
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Figure 66. Read Volatile Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.22 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be ...
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Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 68. Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.24 Write Volatile Enhanced ...
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Figure 69. Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.25 Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the two ...
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Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart ...
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All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, ...
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Table 24. Instruction set: QIO-SPI protocol (page Instruction Description WRNVCR Write NV Configuration Register RDVCR Read Volatile Configuration Register 1000 0101 WRVCR Write Volatile Configuration Register 1000 0001 Read Volatile Enhanced RDVECR Configuration Register Write Volatile Enhanced ...
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Figure 72. Multiple I/O Read Identification instruction and data-out sequence QIO- SPI AFh DQ0 DQ1 DQ2 DQ3 9.3.2 Quad Command Fast Read (QCFR) The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI ...
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Figure 73. Quad Command Fast Read instruction and data-out sequence QSP, 0Bh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7 3 A23-16 A15-8 A7-0 Figure 74. ...
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Figure 75. Quad Command Fast Read instruction and data-out sequence QSP, EBh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7 3 A23-16 A15-8 A7-0 9.3.3 Read ...
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Figure 76. Read OTP instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.4 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same ...
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Figure 79. Quad Command Page Program instruction sequence QIO-SPI, 02h S Mode Mode 0 24-bit address DQ0 DQ1 DQ2 ...
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Figure 81. Quad Command Page Program instruction sequence QIO-SPI, 32h S Mode Mode 0 24-bit address DQ0 DQ1 DQ2 ...
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Figure 82. Program OTP instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.8 Subsector Erase (SSE) For devices with a dedicated part number, at the bottom (or top) of the addressable area there are 8 boot sectors, ...
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Figure 83. Subsector Erase instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.9 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code on the ...
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Figure 86. Program/Erase Suspend instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.12 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Apart form the parallelizing of the ...
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Figure 87. Program/Erase Resume instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.13 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output ...
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Figure 88. Read Status Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.14 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it ...
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Figure 89. Write Status Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.15 Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, ...
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Figure 90. Read Lock Register instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.16 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock ...
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Figure 91. Write to Lock Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.17 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of ...
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Figure 92. Read Flag Status Register instruction sequence QIO-SPI S Mode Mode 0 Instruction DQ0 DQ1 DQ2 DQ3 9.3.18 Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits ...
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Figure 93. Clear Flag Status Register instruction sequence QIO-SPI 9.3.19 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. 152/185 Instruction DQ0 DQ1 DQ2 ...
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Figure 94. Read NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.20 Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. ...
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Figure 95. Write NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.21 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. 154/185 ...
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Figure 96. Read Volatile Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.22 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration ...
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Figure 97. Write Volatile Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.23 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. 156/185 0 1 ...
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Figure 98. Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.24 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the ...
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Figure 99. Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 158/185 Volatile Enhanced Configuration Register In Instruction Quad_Write_VECR ...
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Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as ...
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Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart ...
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... Using the Volatile Configuration Register: this is dedicated to applications that boot in SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life need to switch to XIP mode to directly execute some code in the flash. Using the Non Volatile Configuration Register: this is dedicated to applications that need to boot directly in XIP mode ...
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Figure 102. N25Q128 Read functionality Flow Chart Power On NVCR Check No Is XIP enabled ? Yes XIP mode No Yes XiP Confirmation bit = 0 ? 10.1 Enter XIP mode by setting the Non Volatile Configuration Register To use ...
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Table 25. NVCR XIP bits setting example B1h (WRNVCR + 0110 opcode) 6 dummy cycles for fast read instructions XIP set as default; Quad I/O mode Figure 103. XIP mode directly after power on NVCR check: XIP enabled Vd t ...
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Enter XIP mode by setting the Volatile Configuration Register To use the Volatile Configuration Register method to enter XIP mode necessary to write bit 3 of the Volatile Configuration Register to make the device ...
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Figure 104. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example) S Mode Mode 0 Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ Note the XIP Confirmation ...
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XIP Memory reset after a controller reset If during the application life the system controller is reset during operation, and the device features the RESET functionality (in devices with a dedicated part number), and the feature has not been ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at power-up, and then for a further ...
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Figure 105. Power-up timing, Fast POR selected Vcc V (max) CC Chip selection not allowed V (min) CC Chip reset V WI Figure 106. Power-up timing, Fast POR not selected Vcc V (max) CC Chip selection not allowed V (min) ...
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Fast POR The Fast POR feature is available to speed up the power-on sequence for applications that only require reading the memory after the power on sequence (no modify instructions). If enabled, the Fast POR allows read operations and ...
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... Fast program/erase voltage V Electrostatic discharge voltage (human body model) ESD 1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Avoid applying VPP 3. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the ...
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Table 32. DC Characteristics Symbol Parameter ILI Input leakage current ILO Output leakage current ICC1 Standby current ICC2 Deep Power-down current Operating current (Fast Read Single I/O) ICC3 Operating current (Fast Read Dual I/O) Operating current (Fast Read Quad I/O) ...
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Note: The AC Characteristics data is preliminary. Table 33. AC Characteristics (page Symbol Alt. Clock frequency for the all the fC fC instructions (Extended SPI, DIO-SPI and QIO-SPI protocol) but the READ instruction fR Clock frequency for ...
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Table 33. AC Characteristics (page Symbol Alt. Enhanced program supply voltage High (6) tVPPHSL (VPPH) to Chip Select Low for Single and Dual I/O Page Program tW Write status register cycle time tCFSR Clear flag status register ...
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Table 34. Reset Conditions Symbol Alt. Parameter (1)(2) tRLRH tRST Reset pulse width Reset Recovery (1) tRHSL tREC Time S# deselect to R (1) tSHRV valid tDP tRDP 1. All values are guaranteed by characterization and not 100% tested in ...
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Figure 110. Write protect setup and hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 Figure 111. Hold timing S C DQ1 DQ0 HOLD 176/185 High Impedance tHLCH tCHHL tCHHH tHLQZ tSHWL AI07439c tHHCH tHHQX AI13746 ...
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Figure 112. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN Figure 113. VPP timing DQ0 V PPH V PP tVPPHSL tCH tCLQV tCL End of command (identified by WIP polling) tSHQZ LSB OUT ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Figure 115. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 36. SO16 wide - 16-lead plastic small outline, 300 mils body width, ...
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Figure 116. TBGA - mm, 24-ball, mechanical package outline 1. Drawing is not to scale. 180/185 ...
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Table 37. TBGA 6x8 mm 24-ball package dimensions MIN A A1 0.20 A2 0.79 Øb 0.35 0.40 D 5.90 6.00 D1 4.00 E 7.90 8.00 E1 4.00 eD 1.00 eE 1.00 FD 1. ...
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... Device density 128 = 128 Mbit Technology Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP 4 = Byte addressability, Reset pin, Basic XiP Operating voltage 1 = VCC = 1 Block Structure B = Bottom T = Top E = Uniform (no boot sectors) ...
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... Hold pin, Basic XiP N25Q128A21BF840F N25Q128A11TF840E Byte addressability, Hold pin, Numonyx XiP N25Q128A11TF840F N25Q128A21TF840E Byte addressability, Hold pin, Basic XiP N25Q128A21TF840F N25Q128A11B1240E Byte addressability, Hold pin, Numonyx XiP N25Q128A11B1240F N25Q128A21B1240E Byte addressability, Hold pin, Basic XiP N25Q128A21B1240F N25Q128A11T1240E Byte addressability, Hold pin, Numonyx XiP ...
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Revision history Table 40. Document revision history Date Revision 12-Feb-2010 1.0 184/185 Changes Initial public release. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...