ISPLSI 5256VE-125LT128I Lattice, ISPLSI 5256VE-125LT128I Datasheet - Page 16

• Manufacturer Part Number: ISPLSI 5256VE-125LT128I
• Description: CPLD ispLSI® 5000VE Family 12K Gates 256 Macro Cells 125MHz EECMOS Technology 3.3V 128-Pin TQFP
• Manufacturer: Lattice

Specifications of ISPLSI 5256VE-125LT128I

• Package: 128TQFP
• Family Name: ispLSI® 5000VE
• Device System Gates: 12000
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 9.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 125 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: -40 to 85 °C

1
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for
details.
Routing Adders
Tioi Input Adders
Tioo Output Adders
Tbla Additional Block Loading Adders
ispLSI 5256VE Timing Parameters (continued)
Timing for open drain configurations is the same as non-open drain configurations.
LVCMOS25_out
LVCMOS33_out
ADDER TYPE
Slow Slew I/O
LVTTL_out
clk1
clk2
clk3
t
1
2
3
4
5
6
7
lp
BASE PARAMETER
1
t
t
t
buf,
buf,
buf,
t
t
t
t
buf,
t
t
t
t
t
t
t
t
gclk_in
gclk_in
gclk_in
route
route
route
route
route
route
route
route
t
t
t
en,
en,
en,
t
en
t
t
t
dis
dis
dis
-165
1.0
1.4
1.4
1.4
4.0
0.0
0.5
0.0
0.1
0.1
0.2
0.3
0.4
0.4
0.5
16
Specifications ispLSI 5256VE
-125
1.5
1.7
1.7
1.7
4.0
0.0
0.5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
ADDER
-100
1.5
1.7
1.7
1.7
4.0
0.0
0.5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-80
1.5
1.7
1.7
1.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
4.0
0.0
0.5
0.0
Timing Table/5256VE
Timing v.2.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns