AD5530BRU Analog Devices Inc, AD5530BRU Datasheet - Page 6

• Manufacturer Part Number: AD5530BRU
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRU

• Rohs Status: RoHS non-compliant
• Settling Time: 20µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

AD5530/AD5531
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
V
otherwise noted.
Table 5.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
(READBACK)
MAX
1
2
3
4
5
6
7
8
12
13
14
15
16
17
Guaranteed by design, not subject to production test.
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with t
90% of V
SDO; R
DD
CHAINING)
(DAISY-
= 10.8 V to 16.5 V, V
RBEN
SCLK
SYNC
SDIN
PULLUP
SDO
SDO
DD
) and timed from a voltage level of (V
= 5 kΩ, C
1, 2, 3
L
= 15 pF
t
6
Limit at T
2
500
200
200
50
40
50
40
15
50
130
50
50
50
100
SS
MSB
= −10.8 V to −16.5 V; GND = 0 V; R
t
4
DB15
MIN
, T
MAX
DB14
IL
Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode
+ V
IH
)/2.
t
7
DB11
t
1
t
8
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Rev. B | Page 6 of 20
L
= 5 kΩ and C
LSB
DB0
t
t
5
13
t
MSB
3
DB15
Description
SCLK frequency
SCLK cycle time
SCLK low time
SCLK high time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Min SYNC high time
Data setup time
Data hold time
CLR pulse width
SCLK falling edge to SDO valid
SCLK falling edge to SDO invalid
RBEN to SCLK falling edge setup time
RBEN hold time
RBEN falling edge to SDO valid
t
2
L
= 220 pF to GND. All specifications T
t
15
t
17
DB11
t
14
MSB
0
t
13
0
DB0
LSB
t
16
RB13
MIN
R
= t
to T
F
= 5 ns (10% to
MAX
t
14
, unless
RB0
LSB