ATF1502ASV-15AU44 Atmel, ATF1502ASV-15AU44 Datasheet - Page 7

• Manufacturer Part Number: ATF1502ASV-15AU44
• Description: IC CPLD EE HP 15NS 44-TQFP
• Manufacturer: Atmel
• Series: ATF1502ASVr

Specifications of ATF1502ASV-15AU44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Family Name: ATF1502ASV
• # Macrocells: 32
• Number Of Usable Gates: 750
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 32
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant

4. Power-up Reset
5. Security Fuse Usage
6. Programming
1615J–PLD–01/06
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-
rocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins, with
reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned
on), the reduced-power adder, t
data paths t
The ATF1502ASV macrocell also has an option whereby the power can be reduced on a per-
macrocell basis. By enabling this power-down option, macrocells that are not used in an applica-
tion can be turned down, thereby reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
The ATF1502ASV is designed with a power-up reset, a feature critical for state machine initial-
ization. At a point delayed slightly from V
state of each output will depend on the polarity of its buffer. However, due to the asynchronous
nature of reset and uncertainty of how V
are required:
The ATF1502ASV has two options for the hysteresis about the reset level, V
Large. To ensure a robust operating environment in applications where the device is operated
near 3.0V, Atmel recommends that during the fitting process users configure the device with the
Power-up Reset hysteresis set to Large. For conversions, Atmel POF2JED users should include
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is added:
When the Large hysteresis option is active, I
well.
A single fuse is provided to prevent unauthorized copying of the ATF1502ASV fuse patterns.
Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains
accessible.
ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG proto-
col. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving the
3. The clock must remain stable during T
4. If V
clock pin high, and,
CC
CC
LAD
falls below 2.0V, it must shut off completely before the device is turned on again.
rise must be monotonic,
, t
LAC
, t
IC
, t
ACL
, t
ACH
RPA
and t
, must be added to the AC parameters, which include the
SEXP
CC
CC
.
crossing V
actually rises in the system, the following conditions
D
.
CC
is reduced by several hundred microamps as
RST
, all registers will be initialized, and the
ATF1502ASV
RST
, Small and
7