ATF1504BE-7AU44 Atmel, ATF1504BE-7AU44 Datasheet - Page 11

• Manufacturer Part Number: ATF1504BE-7AU44
• Description: IC CPLD 64MC 1.8V 44-TQFP
• Manufacturer: Atmel
• Series: ATF1504BEr

Specifications of ATF1504BE-7AU44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Macrocells: 64
• Number Of I /o: 32
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Features: CMOS/TTL Compatible
• Voltage: 1.8V
• Memory Type: CMOS
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

5.1
5.2
3637B–PLD–1/08
In-System Configuration – ISC (Also Referred to as ISP)
On-the-Fly Reconfiguration – OTF
This mode is the de-facto standard used to program the CPLD when it is attached to a PCB. The
term ISC can also be used interchangeably with ISP (In-system Programming). ISC or ISP elim-
inates the need for an external device programmer, and the devices can be soldered to a PCB
without being preprogrammed.
In the ISC mode, the logic operation of the ATF1504BE is halted and the embedded configura-
tion memory is programmed. The device is programmed by first erasing the configuration
memory in the CPLD and then loading the new configuration data into the memory, which in-turn
configures the PLD for functional mode. When the device is in the ISC programming mode, all
user I/Os are held in the high impedance state.
The ISC mode is best suited for working with the ATF1504BE device in a design development or
production environment. Configuration of the ATF1504BE device done via a Download Cable
(see
this mode, the PC is typically the controlling device that communicates with the CPLD.
Figure 5-1.
In this mode, the CPLD design pattern stored in the internal configuration memory can be modi-
fied while the previously-programmed design pattern is operating with minimal disturbance to
the programming operation of the new design. The new configuration will take affect after the
OTF programming process is completed and the OTF mode is exited.
The configuration data for any design is stored in the internal configuration memory. Once the
configuration data is transferred to the internal static registers of the CPLD, the CPLD operates
with the design pattern and the configuration memory is free to be re-loaded with a new set of
configuration data. The design pattern due to the new configuration content is activated through
an initialization cycle that occurs on exiting the OTF mode or after the next power up sequence.
Figure 5-2
mode. The processor is the controlling device that communicates with the CPLD and uses con-
figuration data stored in the external memory to configure the CPLD.
Figure 5-1 on page
shows the electrical interface for configuration of the ATF1504BE device in the OTF
Configuration of ATF1504BE Device Using a Download Cable
CPLD Device
ATF1504BE
11) is the default mode used to program the device in the ISC mode. In
TDO
TMS
TCK
TDI
Cable to 10-pin
ISP Download
JTAG Header
Connector
1
3
5
7
9
Connect
JTAG
2
4
6
8
10
ATF1504BE
V
CC
11