ATF1504BE ATMEL Corporation, ATF1504BE Datasheet
ATF1504BE
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ATF1504BE Summary of contents
Page 1
... Advanced Digital CMOS Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20-year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity • Security Fuse Feature • Hot-Socketing Supported High- performance CPLD ATF1504BE 3637A–PLD–11/06 ...
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... The ATF1504BE’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504BE has bi-directional I/O pins and four dedicated input pins. Each dedi- cated pin can also serve as a global control signal, register clock, register reset or output enable. ...
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... TQFP Top View VCCIOA 3 I/O/TDI I I/O 8 I/O 9 I/O 10 GND 11 12 I/O 13 I/O 14 I/O/TMS 15 I/O 16 I/O 17 VCCIOA 18 I/O 19 I I/O 25 ATF1504BE 75 I/O 74 GND 73 I/O/TDO I I/O 68 I/O 67 I/O 66 VCCIOB 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O/VREFB 59 GND 58 I/O 57 I I/O 51 ...
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... Figure 1-2. ATF1504BE 4 44-lead TQFP Top View I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCCIOA 9 I I/O 32 I/O/TDO 31 I/O 30 I/O 29 VCCIOB 28 I/O 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O 3637A–PLD–11/06 ...
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... The User Signature is accessible regardless of the state of the security fuse. The ATF1504BE device is an In-System Programming (ISP) device. It uses the industry-stan- dard 4-pin JTAG interface (IEEE Std. 1532), and is fully compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board ...
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... OR/XOR/CASCADE Logic The ATF1504BE’s logic structure is designed to efficiently support all types of logic. Within a sin- gle macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with minimal additional delay. The macrocell’ ...
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... Flip-flop The ATF1504BE’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial out- put macrocell ...
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... Programmable Pin-keeper Option for Inputs and I/Os The ATF1504BE offers the option of programming each of its input or I/O pin so that pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and sys- tem noise ...
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... I/O Bank The I/O pins of the ATF1504BE are grouped into two banks, Bank A and Bank B. Bank A com- prises of I/O pins for macrocells (Logic Block A and B), and it is powered comprises of I/O pins for macrocells (Logic Block C and D), and it is powered by V ...
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... JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. When using the ISP hardware or software to program the ATF1504BE devices, four I/O pins must be reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O pins are still available to the design for buried logic functions ...
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... PLD for functional mode. When the device is in the ISC programming mode, all user I/Os are held in the high impedance state. The ISC mode is best suited for working with the ATF1504BE device in a design development or production environment. Configuration of the ATF1504BE device done via a Download Cable ...
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... ISP Programming Protection The ATF1504BE has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. ...
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... JTAG Boundary-scan Cell (BSC) Testing The ATF1504BE contains 64 I/O pins and four input pins. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1532. A typical BSC consists of three capture registers or scan registers and up to two update registers ...
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... Figure 6-2. 7. Design Software Support ATF1504BE designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages such as VHDL party synthesis and simulation tools from Mentor Graphics tools. ATF1504BE 14 BSC Configuration for Macrocell TDO TDI ...
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... Max Units ATF1504BE Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
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... Input High-voltage IH V Output Low-voltage OL V Output High-voltage OH LVCMOS = 2.5V V Input Low-voltage IL V Input High-voltage IH V Output Low-voltage OL V Output High-voltage OH LVCMOS = 1.8V V Input Low-voltage IL ATF1504BE 16 Condition V = 1.8V 3.3V, CCINT CCIO MHz V = 1.8V 3.3V, CCINT CCIO MHz V = 1.8V 3.3V, CCINT CCIO MHz V = 1.8V 3.3V, CCINT ...
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... LD mA 1.4V OH CCIO Conditions mA 2.3V OH CCIO mA 2.3V OL CCIO may not exceed ± should track the variations in V REF REF REF of receiving devices. REF ATF1504BE Min Typ Max 0. 3.9 CCIO 0.45 0 0.45V CCIO V - 0.45V CCIO -0.3 0.7 1.3 0.45 0 0.45V CCIO Min Typ Max 2 ...
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... Input Low Voltage IL(DC) Notes: 1. Peak-to-peak noise on V REF transmitting device must track Timing Model Input Delay t IN Switch Matrix t UIM ATF1504BE 18 Conditions mA CCIO mA 2.3V OL CCIO may not exceed ± should track the variations in V REF REF of receiving devices ...
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... Note: 3637A–PLD–11/06 V CCIO R 1 Device Under Test 350 Ohm 300 Ohm 200 Ohm 150 Ohm C includes test fixtures and probe capacitance. L ATF1504BE Test Point 350 Ohm 35 pF 300 Ohm 35 pF 200 Ohm 35 pF 150 Ohm ...
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... Cascade Logic Delay PEXP t Logic Array Delay LAD t Logic Control Delay LAC t Internal Output Enable Delay IOE Output Buffer Delay (HD) t OD1 (High Drive pF) L Output Buffer Enable Delay t ZX1 (High Drive pF) L ATF1504BE 20 -5 Min Max 5.0 7 4.2 2 0.5 6 1.25 1.25 1.7 0.50 6.5 1.75 1.75 3 333 4 250 0 ...
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... These delays apply to all I/O PINS when used as inputs/aysynchronous clock. 3. SSTL is not supported for low drive output (LD). 3637A–PLD–11/06 (1) Min V = 1.5V CCIO V = 1.8V CCIO V = 2.5V CCIO V = 3.3V CCIO = 5 pF) L 1.7 0.5 0.5 0 1.5V CCIO V = 1.8V Level CCIO CCIO V = 2.5V CCIO V = 3.3V CCIO V = 2.5V CCIO V = 3.3V CCIO V = 2.5V CCIO V = 3.3V CCIO ATF1504BE -5 -7 Max Min Max 6.0 7.0 5.5 6.5 4.5 5.5 4.0 5 2.2 0.6 0.6 0.6 0.7 1.2 1.2 1.2 1.8 1.8 2.5 3 1.8 2 1.75 2 1.75 2 0.5 0.8 1.5 2 6.5 8.5 5.5 7.5 5.25 7. 1.5 1.5 1.5 1 ...
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... Power-down Mode The ATF1504BE includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur- rent is reduced to less than 100 µA. During power-down, all output data and internal logic states are latched and held ...
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... ATF1504BE Dedicated Pinouts Table 13-1. Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O /GCLK3 I (1,2) I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND V CCINT V CCIOA V CCIOB N Signal Pins # User I/O Pins OE (1, 2) GCLR GCLK ( (1, 2) TDI, TMS, TCK, TDO GND V CCINT V CCIOA V CCIOB 3637A– ...
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... PD1 TDI 32/ TMS ATF1504BE 24 ATF1504BE I/O Pinouts 100-lead PLC TQFP 100 ...
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... OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE (VCCINT = 1.8V, VCCIO = 1.5-3.3V 25C), High Drive 0 -20 -40 1.5V 1.8V -60 2.5V 3.3V -80 -100 -120 OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE (VCCINT = 1.8V, VCCIO =1.5-3.3V 25C), Low Drive 0 -5 1.5V -10 1.8V 2.5V -15 3.3V -20 -25 ATF1504BE icc_int_vccio_3.3V icc_io_vccio_1.8V icc_io_vccio_2.5V icc_io_vccio_3.3v iccio_vccio_1.5V 0.5 1 1.25 2.5 5 FREQUENCY (HZ) OUTPUT VOLTAGE ( V ) OUTPUT VOLTAGE ( V ) 1.5V 1.8V 2.5V 3.3V 1.5V 1.8V 2.5V 3.3V 25 ...
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... I/O PIN CURRENT VS. I/O PIN VOLTAGE I/O PIN (VCCINT = 1.8V, VCCIO = 1.5V-3.3V 25C) (PIN KEEPER ON) 200 150 100 50 0 -50 -100 -150 I/O PIN VOLTAGE ( V ) Icc_int, Icc_io(LD) Vs Frequency Per Lab 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.1 0.2 0.5 1 1.25 FREQUENCY (MHZ) ATF1504BE 26 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 0 7.2 7.0 6.8 6.6 6.4 6.2 1.5V 6.0 1.8V 5.8 2.5V 5.6 3.3V 5.4 5.2 5.0 4 icc_int_Vccio_3.3V 8 icc_io_Vccio_1 ...
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... Thin Plastic Gull Wing Quad Flatpack (TQFP) 100A 100-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 3637A–PLD–11/06 Package 100A 100A 44A 44A Package Type ATF1504BE Operation Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1504BE 28 B PIN 1 IDENTIFIER ...
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... Orchard Parkway San Jose, CA 95131 R 3637A–PLD–11/06 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1504BE A2 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Mentor Graphics ® Corporation. Verilog is the registered trademarks of Cadence Design Systems, Inc ...