ATF1504BE ATMEL Corporation, ATF1504BE Datasheet - Page 13

• Manufacturer Part Number: ATF1504BE
• Description: High Speed CPLD
• Manufacturer: ATMEL Corporation

6. JTAG-BST/ISP Overview
6.1
3637A–PLD–11/06
JTAG Boundary-scan Cell (BSC) Testing
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1504BE. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
i s a u t o m a t i c a l l y r e s e t a t p o w e r - u p . T h e f i v e J T A G m o d e s s u p p o r t e d i n c l u d e :
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1504BE’s ISP can be
fully described using JTAG’s BSDL as described in IEEE Standard 1149.1. This allows
ATF1504BE programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1504BE has the option of using four JTAG-standard I/O pins for boundary-scan testing
(BST) and ISP purposes. The ATF1504BE is programmable through the four JTAG pins using
the IEEE standard JTAG programming protocol established by IEEE Standard 1532 using 1.8V
LVCMOS level programming signals from the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
The ATF1504BE contains 64 I/O pins and four input pins. Each input pin and I/O pin has its own
boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1532. A typical BSC consists of three capture registers or scan registers and up
to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the
macrocells. The BSCs in the device are chained together through the capture registers. Input to
the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by the
JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown
below.
Figure 6-1.
Note:
The ATF1504BE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
ATF1504BE
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