CY37064VP44-100AXC Cypress Semiconductor Corp, CY37064VP44-100AXC Datasheet - Page 18

• Manufacturer Part Number: CY37064VP44-100AXC
• Description: IC CPLD 64 MACROCELL 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37064VP44-100AXC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 12.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 64
• Number Of I /o: 37
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Voltage: 3.3V
• Memory Type: CMOS
• Family Name: Ultra37000
• # Macrocells: 64
• Number Of Usable Gates: 2000
• Frequency (max): 100MHz
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 37
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1937; CY37064VP44-100AXC

Document #: 38-03007 Rev. *E
Switching Characteristics
Product Term Clocking Parameters
t
t
t
t
t
t
Pipelined Mode Parameters
t
Operating Frequency Parameters
f
f
f
f
Reset/Preset Parameters
t
t
t
t
t
t
User Option Parameters
t
t
t
t
t
t
f
COPT
SPT
HPT
ISPT
IHPT
CO2PT
ICS
MAX1
MAX2
MAX3
MAX4
RW
RR
RO
PW
PR
PO
LP
SLEW
3.3IO
S JTAG
H JTAG
CO JTAG
JTAG
JTAG Timing Parameters
[13]
[13]
[13, 14, 15]
[13, 14, 15]
[13]
[13]
Parameter
[13, 14, 15]
[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Input Register Synchronous Clock (CLK
Clock (CLK
Maximum Frequency with Internal Feedback (Lesser of 1/t
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
1/(t
Maximum Frequency with External Feedback (Lesser of 1/(t
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
or 1/t
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Asynchronous Reset to Output
Asynchronous Preset Width
Asynchronous Preset Recovery Time
Asynchronous Preset to Output
Low Power Adder
Slow Output Slew Rate Adder
3.3V I/O Mode Timing Adder
Set-up Time from TDI and TMS to TCK
Hold Time on TDI and TMS
Falling Edge of TCK to TDO
Maximum JTAG Tap Controller Frequency
S
+ t
SCS
H
), or 1/t
)
[5]
0
, CLK
Over the Operating Range (continued)
CO
1
)
, CLK
[5]
2
, or CLK
[5]
[5]
[5]
[5]
[5]
3
)
[5]
[5]
[5]
0
, CLK
[5]
Description
1
, CLK
[12]
2
, or CLK
CO
+ t
SCS
CO
IS
), 1/t
, 1/(t
3
Ultra37000 CPLD Family
+ t
) to Output Register Synchronous
S
ICS
S
) or 1/(t
+ t
, 1/(t
H
), or 1/t
WL
WL
+ t
+ t
CO
WH
WH
)
WL
[5]
), 1/(t
)
[5]
+ t
IS
WH
Page 18 of 64
+ t
),
IH
),
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns