XC9572-15PCG84C Xilinx Inc, XC9572-15PCG84C Datasheet - Page 5

• Manufacturer Part Number: XC9572-15PCG84C
• Description: IC CPLD 72MCRCELL 15NS 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC9572-15PCG84C

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 72
• Number Of Gates: 1600
• Number Of I /o: 69
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 5V
• Memory Type: FLASH
• Cpld Type: FLASH
• No. Of Macrocells: 72
• No. Of I/o's: 72
• Propagation Delay: 15ns
• Global Clock Setup Time: 8ns
• Frequency: 55.6MHz
• Supply Voltage Range: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1444

Macrocell
Each XC9500 macrocell may be individually configured for
a combinatorial or registered function. The macrocell and
associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable. The product
DS063 (v5.5) June 25, 2007
Product Specification
36
R
Figure
Figure 3: XC9500 Macrocell Within Function Block
Allocator
Product
Term
3.
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
www.xilinx.com
Set/Reset
Global
term allocator associated with each macrocell selects how
the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Clocks
3
Global
XC9500 In-System Programmable CPLD Family
D/T
R
S
Q
OUT
PTOE
To
Fast CONNECTII
Switch Matrix
DS063_03_110501
To
I/O Blocks
5