XC9572-15PCG84C Xilinx Inc, XC9572-15PCG84C Datasheet - Page 6

• Manufacturer Part Number: XC9572-15PCG84C
• Description: IC CPLD 72MCRCELL 15NS 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC9572-15PCG84C

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 72
• Number Of Gates: 1600
• Number Of I /o: 69
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 5V
• Memory Type: FLASH
• Cpld Type: FLASH
• No. Of Macrocells: 72
• No. Of I/o's: 72
• Propagation Delay: 15ns
• Global Clock Setup Time: 8ns
• Frequency: 55.6MHz
• Supply Voltage Range: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1444

XC9500 In-System Programmable CPLD Family
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
6
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
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term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
DS063 (v5.5) June 25, 2007
D/T
S
R
Product Specification
Macrocell
DS063_04_110501
R