CY37032P44-125AXC Cypress Semiconductor Corp, CY37032P44-125AXC Datasheet - Page 32

• Manufacturer Part Number: CY37032P44-125AXC
• Description: IC CPLD 32 MACROCELL 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37032P44-125AXC

• Number Of Macrocells: 32
• Package / Case: 44-LQFP
• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of I /o: 37
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Features: Programmable
• Voltage: 5V
• Memory Type: CMOS
• Number Of Product Terms Per Macro: 16
• Maximum Operating Frequency: 125 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 37
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• No. Of Macrocells: 32
• No. Of I/o's: 37
• Propagation Delay: 6ns
• Frequency: 125MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Family Name: Ultra 37000
• # Macrocells: 32
• Number Of Usable Gates: 960
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 37
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2901; CY37032P44-125AXC

Document #: 38-03007 Rev. *E
Pin Configurations
Note:
Note:
20. For 3.3V versions (Ultra37000V), V
21. This pin is a N/C, but Cypress recommends that you connect it to V
I/O
10
CLK
CLK
V
/TCK
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
CCO
I/O
I/O
I/O
0
1
/I
/I
11
12
13
14
15
16
17
18
19
20
21
22
23
[20]
0
1
8
9
(continued)
23
24
25
26
27
28
29
30
31
32
12
13
14
15
16
17
18
19
20
21
22
CCO
33
11
= V
34
10
CC
C
D
A
B
E
F
35
.
9
CLK
JTAG
CLK
36
I/O
TCK
TMS
I/O
V
1
CC
8
2
0
13
5
/ I
/ I
EN
37
0
1
7
48-ball Fine-Pitch BGA (BA50)
38
I/O
V
I/O
I/O
I/O
V
84-lead PLCC (J83) / CLCC (Y84)
2
CC
CC
6
12
4
7
8
39
5
40
I/O
I/O
I/O
I/O
I/O
I/O
3
11
14
4
3
2
6
9
CC
41
to ensure future compatibility.
3
Top View
GND
GND
I/O
I/O
42
I/O
I/O
4
Top View
10
15
1
0
2
43
1
I/O
I/O
GND
GND
I/O
I/O
44 45
5
31
29
16
17
84
83
I/O
I/O
I/O
I/O
I/O
I/O
46
6
30
28
25
22
20
18
82
47
81
I/O
I/O
I/O
I/O
V
V
48
7
CC
CC
26
24
23
21
80 79
49
CLK
CLK
I/O
I/O
TDO
V
TDI
I
8
CC
50
3
1
3
27
19
/ I
/ I
Ultra37000 CPLD Family
78
4
2
51
77
52
76
53
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK
GND
V
CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CCO
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
3
2
/I
/I
/TDI
4
3
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