XCR3032XL-7VQ44C Xilinx Inc, XCR3032XL-7VQ44C Datasheet - Page 9

• Manufacturer Part Number: XCR3032XL-7VQ44C
• Description: IC ISP CPLD 32 MCELL3.3V 44-VQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner XPLA3r

Specifications of XCR3032XL-7VQ44C

• Programmable Type: In System Programmable (min 1K program/erase cycles)
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 32
• Number Of Gates: 750
• Number Of I /o: 36
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 CPLD Data Sheets and Application
Notes
Revision History
The following table shows the revision history for this document.
DS023 (v2.2) September 15, 2008
Product Specification
11/18/00
02/05/01
04/11/01
04/19/01
08/27/01
01/08/02
01/06/03
07/15/03
08/21/03
02/13/04
04/08/05
03/31/06
09/15/08
Date
R
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
Initial Xilinx release.
Removed Timing Model.
Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers,
Table 1
I/O; changed V
Updated Typical I/V curve,
Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical
Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial
packages. Added 200 MHz to
to 0.5 ns.
Updated T
renamed T
to more closely resemble true test conditions, added note for T
measurement.Updated note 5 in AC Characteristics table lowering typical current draw
during configuration.
Added voltage and temperature to
adding T
Information format.
Updated Device Part Marking. Updated test conditions for I
Updated Package Device Marking Pin 1 orientation.
Add solder temperature specification. Add links to data sheets, application notes and
packages.
Added I
about Pb-free packages.
Added Warranty Disclaimer; Added Pb-Free ordering information.
Added notes to tables to indicate PC44 and PCG44 packages are obsolete. Removed part
number references to the obsolete PC44C and PCG44C packages in the
Combination
and updated
CCSB
PTCK
HI
SU
spec to correct a typo. Added single p-term setup time (T
Typical and T
to T
parameter to internal timing model. Increased -5 F
Information. See Product Discontinuation Notice
OH
SU2
spec.
Figure
for setup time through the OR array. Updated AC Load Circuit diagram
www.xilinx.com
APRPW
Figure
1. Added Typical I/V curve,
Figure 1
Device Packages
Device Package User Guide
specifications. Removed T
2: added voltage levels.
Figure
and
Revision
2. Increased -5 T
Table
1. changed -5 F
Figure
XCR3032XL 32 Macrocell CPLD
PCO
IL
SOL
and I
2; added
POD
to 6.0 (from 5.5 ns) by
SYSTEM
specification. Added note
xcn07022.pdf
MAX
IH
delay
.
. Updated Ordering
SU1
Table
to 200 MHz, -5 T
) to AC Table,
Ordering
2: Total User
.
F
9