XCR3032XL-10 XILINX [Xilinx, Inc], XCR3032XL-10 Datasheet

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XCR3032XL-10

Manufacturer Part Number
XCR3032XL-10
Description
XCR3032XL 32 Macrocell CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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DS023 (v1.6) June 27, 2002
Features
Table 1: I
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
Lowest power 32 macrocell CPLD
5.0 ns pin-to-pin logic delays
System frequencies up to 200 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
-
-
-
Optimized for 3.3V systems
-
-
-
-
Advanced system features
-
-
-
-
-
-
-
-
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Frequency (MHz)
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Typical I
48-ball CS BGA (36 user I/O pins)
44-pin VQFP (36 user I/O)
44-pin PLCC (36 user I/O)
Ultra-low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
CC
vs. Frequency (V
CC
(mA)
R
0.02
CC
0
= 3.3V, 25°C)
0.13
1
0.54
0
0
www.xilinx.com
1-800-255-7778
5
14
1.06
XCR3032XL 32 Macrocell CPLD
Preliminary Product Specification
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25 C).
10
Figure 1: I
20
15
10
5
0
0
and
2.09
20
20
Table 1
CC
40
vs. Frequency at V
5.2
50
showing the I
60
Frequency (MHz)
80
10.26
100
100
CC
120
vs. Frequency of our
CC
20.3
200
140
= 3.3V, 25°C
160
DS023_01_080101
180 200
1

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XCR3032XL-10 Summary of contents

Page 1

... Preliminary Product Specification 0 14 Description The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz. ...

Page 2

... XCR3032XL 32 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter (2) V Output High voltage OH V Output Low voltage OL (4) I Input leakage current IL (4) I I/O High-Z leakage current IH I Standby current CCSB (5,6) I Dynamic current CC (7) C Input pin capacitance IN C Clock input capacitance ...

Page 3

... These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS023 (v1.6) June 27, 2002 Preliminary Product Specification -5 Min. Max. 4.5 (3) 5.0 3.5 2.5 - 3 2 200 - 7.2 (6) - 7.2 - 6.0 - 6.5 ) for recommended operating conditions. www.xilinx.com 1-800-255-7778 XCR3032XL 32 Macrocell CPLD (1,2) -7 -10 Min. Max. Min. Max. Unit - 7.0 - 9.1 - 7.5 - 10.0 5.0 - 6.5 3.0 - 3.0 - 4.3 - 5.4 - 4 3.0 - 4.0 - 5 ...

Page 4

... XCR3032XL 32 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast Input buffer delay FIN T Global Clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register, Product Term, and Combinatorial Delays T Latch transparent delay ...

Page 5

... V Figure 3: AC Load Circuit +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified DS023_05_061101 PD2 www.xilinx.com 1-800-255-7778 XCR3032XL 32 Macrocell CPLD Values 390 390 Open Closed Closed Open Closed Closed , pF. Delay measured at + 300 mV, V – ...

Page 6

... Table 3: XCR3032XL I/O Pins Function Block VQ44 CS48 Notes: 1. JTAG pins VQ44 CS48 42 A2 Table 4: XCR3032XL Global, JTAG, Port Enable, Power and No Connect Pins 44 C4 Pin Type (1) ( IN0 / CLK0 2 C2 IN1 / CLK1 3 C1 IN2 / CLK2 5 D3 ...

Page 7

... CS48 Component Availability Pins Type Code XCR3032XL -5 -7 -10 DS023 (v1.6) June 27, 2002 Preliminary Product Specification XCR3032XL - Package 44-pin Plastic Lead Chip Carrier (PLCC) 44-pin Very Thin Quad Flat Pack (VQFP) 48-ball Chip Scale Package 44 44 Plastic PLCC Plastic VQFP PC44 ...

Page 8

... XCR3032XL 32 Macrocell CPLD Revision History The following table shows the revision history for this document. Date Version 11/18/00 1.0 Initial Xilinx release. 02/05/01 1.1 Removed Timing Model. 04/11/01 1.2 Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers, Table 1 I/O; changed V 04/19/01 1.3 Updated Typical I/V curve, 08/27/01 1.4 Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical Characteristics ...

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