DS123 XILINX [Xilinx, Inc], DS123 Datasheet

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... Copyright 2003–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS123 (v2.18) May 19, 2010 Product Specification ...

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... FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGA’s configuration clock. With BUSY Low and CF High, after CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs CE ...

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... Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester simple microprocessor interface that emulates the JTAG DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format, including automatic test equipment ...

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... Table 4: XCFxxP Design Revision Data Security Options Read Protect Reset (default) Reset (default) Set Set DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Write Protection The XCFxxP PROM device also allows the user to write protect (or lock) a particular design revision or PROM option settings ...

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... IR[2] is unused, and is set to '0'. The remaining bits IR[1:0] are set to '01' as defined by IEEE Std. 1149.1. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Platform Flash PROMs. Refer to the IEEE Std. 1149.1 specification for a complete description of Boundary-Scan architecture and the required and optional instructions ...

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... The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the PROM family code a = the specific Platform Flash PROM product the Xilinx manufacturer's ID DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs IR[4] IR[3] ISC Status Security ...

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... TDI setup time when V DIS T TDI hold time when V DIH T TDO valid delay when V DOV DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs TAP Timing Figure 4 These TAP timing characteristics are identical for both Boundary-Scan and ISP operations. T ...

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... Compressed Platform Flash PROM files are created from the target FPGA bitstream(s) using the iMPACT software. Only Slave Serial and Slave DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs SelectMAP (parallel) configuration modes are supported for FPGA configuration when using a XCFxxP PROM programmed with a compressed bitstream ...

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... On the rising edge of CF (when CE is Low). • When reconfiguration is initiated by using the JTAG CONFIG instruction. The data from the selected design revision is then presented on the FPGA configuration interface. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs www.xilinx.com 9 ...

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... JTAG pulses the CF output Low once for 300-500 ns, resetting the FPGA and initiating configuration. The iMPACT software can issue the JTAG CONFIG command to initiate FPGA configuration by setting the “Load FPGA” option. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs PROM 0 PROM 0 ...

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... XCFxxS PROM without damage. Failure to power the PROM correctly while supplying a 5V input signal can result in damage to the XCFxxS device. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs power supply to below the power-down threshold (V ...

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... Revisioning is not enabled, then Reset = address reset to address 0. 5. The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs pull-up resistor is used, but refer to the appropriate FPGA data sheet for the recommended DONE pin pull-up value ...

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... CCINT CCO then the configuration data from the PROM is not available at the recommended threshold levels. The configuration sequence must be delayed until both V and V CCINT CCO DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCF01S, XCF02S, < 2.5V V CCO ≥ 2.5V ...

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... Notes: 1. Input signal transition time measured between 10% V Quality and Reliability Characteristics Symbol T Data retention DR N Program/erase cycles (Endurance Electrostatic discharge (ESD) ESD DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCF01S, XCF02S, XCF04S Min Typ Max 3.0 3.3 3.0 3.3 2.3 2.5 1.7 1 ...

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... Output capacitance OUT Notes: 1. Output driver supply current specification based on no load conditions. 2. TDI/TMS/TCK non-static (active High, OE Low, and TMS/TDI/TCK static. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCF01S, XCF02S, XCF04S Test Min Max Conditions Conditions I = – ...

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... Data hold from CE, OE/RESET, CLK (8) when V = 1.8V CCO CE or OE/RESET to data float delay when V = 3.3V or 2.5V CCO OE/RESET to data float delay when V = 1.8V CCO DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs T CYC ...

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... Guaranteed by design; not tested. 8. CF, EN_EXT_SEL, REV_SEL[1:0], and BUSY are inputs for the XCFxxP PROM only. 9. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCF01S, XCF02S, = 3.3V or 2.5V CCO = 1 ...

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... CE or OE/RESET to data float delay OE/RESET to data float delay OE/RESET to CLKOUT float delay T OECF OE/RESET to CLKOUT float delay CE to CLKOUT float delay T CECF CE to CLKOUT float delay DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs T CYCO CLKO T ...

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... COH Data hold from CLKOUT when V Data hold from CLKOUT when V EN_EXT_SEL setup time to CF, CE, or OE/RESET when V T SXT EN_EXT_SEL setup time to CF, CE, or OE/RESET when V DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Description = 3.3V or 2.5V CCO = 1.8V CCO = 3 ...

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... CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7 kΩ pull- CCO 11. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Description = 3.3V or 2.5V CCO = 1 ...

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... CE hold time (guarantees counters are reset) T HCE CE hold time (guarantees counters are reset) OE/RESET hold time (guarantees counters are reset) T HOE OE/RESET hold time (guarantees counters are reset) DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs ...

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... CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7 kΩ pull- CCO 12. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Description = 3.3V or 2.5V CCO = 1 ...

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... PROMs and to avoid contention on the data lines following configuration, the minimum period is increased based on the CE to CEO and CE to data propagation delays minimum = CYC OCE maximum = CAC OCK CE DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs T CDF T CODF Last Bit T OCK T COCE XCF01S, XCF02S, Min (2,3) – ...

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... Mode Select TCK – TDI – Data In DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Xilinx Package Pin Description D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. The D0 output is set to a high- impedance state during ISPEN (when not clamped). ...

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... CE Figure 11: VO20/VOG20 Pinout Diagram (Top View) with Pin Names DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Pin Description JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50 kΩ ...

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... Data In 10 Data Out CF 09 Output Enable DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Pin Description D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. D0-D7 are the DATA output pins to provide parallel data for configuring a Xilinx FPGA in SelectMap (parallel) mode ...

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... TDI – Data In TDO – Data Out DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Pin Description Chip Enable Output. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the ...

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... TDO 22 GND 23 VCCJ 24 Figure 12: VO48/VOG48 Pinout Diagram (Top View) with Pin Names DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Pin Description – +1.8V Supply. Positive 1.8V supply voltage for internal logic. +3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V – supply voltage connected to the output voltage drivers and input buffers ...

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... G5 C6 VCCO CEO H2 D3 DNC H3 D4 DNC VCCO H6 DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCFxxP FS48/FSG48 Pinout Diagram X-Ref Target - Figure 13 Pin Name VCCINT TMS A DNC B DNC TDO E GND F G DNC H ...

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... VG = 20-pin TSSOP Package, Pb-free (VOG20) XCF32P VO48 = 48-pin TSOP Package (VO48) VOG48 = 48-pin TSOP Package, Pb-free (VOG48) F48 = 48-pin TFBGA Package (FS48) FG48 = 48-pin TFBGA Package, Pb-free (FSG48) DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCF04S VO20 C Operating Range/Processing C = Industrial (T ...

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... Country of Origin Note: In Figure 15 and Figure 16, the two-digit traceability code on the bottom line between the country of origin and date code is not present on all devices. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs XCF04S™ YWW XXX TSSOP Pin 1 Figure 14: 20-Pin TSSOP Marking XCF32P™ ...

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... Section • (Continued on next page) • Section • Section • Section • DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Table 13: • For VO48 package, removed 38 from VCCINT and added it to VCCO. • For FS48 package, removed pin D6 from VCCINT and added it to VCCO. ...

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... Update to the first paragraph of • Added JTAG cautionary note to • Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under • Sections DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Figure 6, page 16, and Figure 7, page 17: Corrected connection name for FPGA DOUT (OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT to DIN. " ...

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... Moved “ MHz” from FPGA Configuration Interface bullets in • • Added statement about ignoring non-JTAG input pins to second paragraph of • Added reference to Platform Flash PROM User Guide in DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Figure 6, page ...

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... PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS123 (v2.18) May 19, 2010 Product Specification Platform Flash In-System Programmable Configuration PROMs Conditions," page 14, " ...