XC3S200 XILINX [Xilinx, Inc], XC3S200 Datasheet
XC3S200
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XC3S200 Summary of contents
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R DS073 (v1.12) November 13, 2008 Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of ® Xilinx FPGA devices • Simple interface to the FPGA • Cascadable for storing longer or multiple bitstreams • Programmable reset ...
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R X-Ref Target - Figure 1 RESET OE/ RESET CLK Figure 1: Simplified Block Diagram for XC17V04, XC17V02 X-Ref Target - Figure RESET OE/ RESET CLK BUSY Figure 2: Simplified Block ...
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R Pin Description DATA[0:7] The array data value corresponding to the internal address counter location is output on enabled DATA[0-7] output pin(s) when CE is active active, and the internal address counter has not incremented beyond its Terminal ...
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R Table 1: Pinouts for XC17V16 and XC17V08 Pin Name 44-pin VQFP (VQ44 16, 17, 26, 36 Notes: 1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Capacity Table ...
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R Capacity Table 4: Device Capacities Devices Configuration Bits XC17V04 (1) XC17V02 XC17V01 Notes: 1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Pinout Diagrams for XC17V04, XC17V02 and XC17V01 ...
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... XC3S50 XC17V04 XC3S200 XC17V04 XC3S400 XC17V04 (1) XC17V08 XC3S1000 XC17V16 XC3S1500 (1) XC17V08 XC17V16 XC3S2000 XC17V16 XC17V16 XC3S4000 (1) XC17V16+XC17V08 XC3S5000 2 of XC17V16 Notes XC17V16 1. Specific part number and package combinations have been discontinued. Refer to XCN07010. For some devices, the XC17V01 original PROM recommendation is shown along with the replacement PROM ...
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R Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the PROM(s) drives the configuration data input(s) of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). ...
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R Table 6: Truth Table for XC17V00 Control Inputs Control Inputs (1) RESET CE Inactive Low Active Low Inactive High Active High Notes: 1. The XC17V00 RESET input has programmable polarity terminal count, highest address value. DS073 ...
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R X-Ref Target - Figure 3 DOUT V CC 4.7K FPGA (1) Modes DIN CCLK DONE INIT PROGRAM (Low Resets the Address Pointer) (1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide. (2) For ...
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R Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to High-Z output TS T Storage temperature (ambient) STG T Junction ...
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R AC Characteristics over Operating Condition for XC17V04, XC17V02, and XC17V01 X-Ref Target - Figure 4 CE RESET/OE CLK T CE DATA Notes: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram ...
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R AC Characteristics over Operating Condition for XC17V16 and XC17V08 X-Ref Target - Figure SCE (1) RESET/OE CLK DATA (2) BUSY Note: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input ...
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R AC Characteristics over Operating Condition When Cascading X-Ref Target - Figure 6 RESET/OE CE CLK DATA CEO Notes: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity. ...
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R Valid Ordering Combinations XC17V16VQ44C XC17V16PC44C XC17V16VQ44I XC17V16PC44I Marking Information Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package ...
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R Revision History The following table shows the revision history for this document. . Date Version 07/26/00 1.0 Initial Xilinx release. 10/09/00 1.1 Updated 20-pin PLCC Pinouts. 11/16/00 1.2 Updated pinouts for XC17V16 and XC17V08, I and C OUT 02/20/01 ...