DS705 XILINX [Xilinx, Inc], DS705 Datasheet
DS705
Related parts for DS705
DS705 Summary of contents
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... Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS705 (v1.1) January 20, 2009 Product Specification ...
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... Digital Clock Manager (DCM) Blocks provide self- calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet For information regarding reliability qualification, refer to RPT103, Xilinx Spartan-3A Family Automotive Qualification Report and RPT070, Spartan-3A Commercial Qualification Report ...
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... Byte Peripheral Interface (BPI) Up from an industry- standard x8 or x8/x16 parallel NOR Flash • Slave Serial, typically downloaded from a processor • Slave Parallel, typically downloaded from a processor DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet IOBs DCM • ...
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... The table also lists the earliest speed file version Table 3: XA Spartan-3A DSP FPGA Family Production Status (Production Speed File) Temperature Range Speed Grade Part Number DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet • HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications • ...
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... XA3SD1800A -4 Standard Performance XA3SD3400A Notes: 1. The XA Spartan-3A DSP FPGA product line is available in -4 speed grade only. 2. The XA3SD3400A is available in I-Grade only. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet BGA Ball A1 R SPARTAN R XA3SD1800A Device Type CSG484XGQ#### ...
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... Notes: 1. For soldering guidelines, see UG112, Device Packaging and Thermal Characteristics and XAPP427, Implementation and Solder Reflow Guidelines for Pb-Free Packages. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Absolute Maximum Ratings Stresses beyond those listed under Maximum Ratings might cause permanent damage to the device. These are stress ratings only ...
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... CMOS Configuration Latch (CCL) and RAM data DRINT CCINT V V level required to retain CMOS Configuration Latch (CCL) and RAM data DRAUX CCAUX DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description supply CCINT supply CCAUX ...
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... I/O standards, and 2. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs. 3. Measured between 10% and 90% V DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description I-Grade Q-Grade ...
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... I/O pair. Not available on Input-only pairs. Notes: 1. The numbers in this table are based on the conditions set forth in 2. This parameter is based on characterization. The pull-up resistance R DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Test Conditions Driver high-impedance state ...
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... The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. 5. For information on the power-saving Suspend mode, see XAPP480, Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode typically saves 40% total power consumption compared to quiescent current. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Device ...
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... When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V well as throughout configuration. 6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet (2) for Drivers ...
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... LVCMOS12 2 2 –2 ( –4 ( –6 (5) PCI33_3 1.5 –0.5 DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 12: DC Characteristics of User I/Os Using Single- Ended Standards (Cont’d) Logic Level Characteristics IOSTANDARD Attribute Max (V) Min (V) (4) HSTL_I 0 ...
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... These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter “Using I/O Resources” in UG331 inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The V REF standards do not use V . REF DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet V INP V INN V ...
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... Output voltage measurements for all differential standards are made with a termination resistor (R differential signal pair any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when V CCO DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet V OUTP V ...
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... Device DNA Read Endurance Table 15: Device DNA Identifier Memory Characteristics Symbol Number of READ operations or JTAG ISC_DNA read operations. Unaffected by DNA_CYCLES HOLD or SHIFT operations. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Bank 0 and 2 Bank 0 1/4th of Bourns Part Number ...
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... Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 16: XA Spartan-3A DSP FPGA v1.32 Speed ...
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... Input adjustment from the same table. When the hold time is negative possible to change the data before the clock’s active edge. 4. DCM output jitter is included in all measurements. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Conditions ...
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... T Time from the active transition at the ICLK input IOICKP of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. No Input Delay is programmed. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet IFD_DELAY_ Conditions Device VALUE ...
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... SAMP capture window of package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the an IOB flip-flop appropriate Xilinx Answer Record for application-specific values. • Answer Record DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet IFD_DELAY_ Conditions (2) LVCMOS25 ...
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... Table 11. 2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet IFD_DELAY Conditions _VALUE ...
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... HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 23: Input Timing Adjustments by IOSTANDARD (Cont’d) Add the Convert Input Time from LVCMOS25 to the Following Units Below Signal Standard (IOSTANDARD) ...
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... This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet ...
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... This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet ...
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... QuietIO DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 26: Add the Convert Output Time from Adjustment LVCMOS25 with 12mA Drive and Below Units Fast Slew Rate to the Following ...
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... QuietIO DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet (Cont’d) Table 26: Add the Convert Output Time from Adjustment LVCMOS25 with 12mA Drive and Below Units Fast Slew Rate to the Following ...
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... LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet (Cont’d) ...
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... HSTL_II_18 0.9 HSTL_III_18 1.1 SSTL18_I 0.9 SSTL18_II 0.9 SSTL2_I 1.25 SSTL2_II 1.25 SSTL3_I 1.5 SSTL3_II 1.5 DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet LVCMOS, LVTTL), then R open connection, and V measurement point (V used at the Output. X-Ref Target - Figure 8 and termination , the other T Inputs (V) ...
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... Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Inputs ...
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... Table 28 and Table 29 provide the essential SSO guidelines. For each device/package combination, DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet provides the number of equivalent V equivalent number of pairs is based on characterization and may not match the physical number of pairs. For each ...
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... Fast QuietIO DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 29: Recommended Number of Simultaneously Switching Outputs per V =3.3V) CCAUX Package Type Signal Standard CSG484, FGG676 (IOSTANDARD) Left, Right (Banks 1,3) LVCMOS25 ...
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... PCI33_3 HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 29: Recommended Number of Simultaneously =3.3V) Switching Outputs per V CCAUX Package Type CSG484, FGG676 Signal Standard (IOSTANDARD) Left, Right ...
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... Set/Reset Pulse Width T The minimum allowable pulse width, High or Low, to the CLB’s SR input RPW_CLB Notes: 1. The numbers in this table are based on the operating conditions set forth in DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description Table 8. www.xilinx.com ...
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... Hold time of the data input after the active transition at the CLK input of the SRLDH shift register Clock Pulse Width Minimum High or Low pulse width at CLK input WPH WPL DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description Description www.xilinx.com Speed Grade -4 Units ...
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... Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input Frequency of signals distributed on global buffers (all sides) Notes: 1. The numbers in this table are based on the operating conditions set forth in DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Symbol Minimum T ...
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... Low pulse width of the CLK signal BPWL Clock Frequency F Block RAM clock frequency BRAM Notes: 1. The numbers in this table are based on the operating conditions set forth in DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description Table 8. www.xilinx.com Speed Grade -4 ...
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... The numbers in this table are based on the operating conditions set forth in DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Pre-adder ...
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... The numbers in this table are based on the operating conditions set forth in DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Pre-adder ...
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... CLKIN input jitter beyond these limits might cause the DCM to lose lock. 5. The DCM specifications are guaranteed when both adjacent DCMs are locked. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet change with the addition of DFS or PS functions are ...
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... CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period and 0 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps. 5. The typical delay step size is 23 ps. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description ...
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... CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period and 0 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps. DS705 (v1.1) January 20, 2009 Product Specification ...
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... The DCM_DELAY_STEP values are provided at the bottom of Miscellaneous DCM Timing Table 43: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN Minimum duration of a RST pulse width DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description Description ±[INTEGER(10 • (T CLKIN < 60 MHz ≥ ...
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... T CLK High time DNACLKL T CLK Low time DNACLKH Notes: The minimum READ pulse width is 5 ns, and the maximum READ pulse width is 10 μs. 1. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description www.xilinx.com Min Max Units 1.0 – ...
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... FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512. Notes: 1. These parameters based on characterization. 2. For information on using the Suspend feature, see XAPP480, Using Suspend Mode in Spartan-3 Generation FPGAs. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Exiting Suspend Mode t SUSPENDHIGH_AWAKE t ...
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... Power-on reset and the clearing of configuration memory occurs during this period. 3. This specification applies only to the SPI and BPI modes. 4. For details on configuration, see UG332, Spartan-3 Generation Configuration User Guide. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet 1.0V 2.0V 2 ...
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... CCLK22 T CCLK25 T CCLK27 T CCLK33 T CCLK44 T CCLK50 T CCLK100 Notes: 1. Set the ConfigRate option value when generating a configuration bitstream. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet ConfigRate Temperature Setting Range 1 I-Grade/ (power-on value) Q-Grade I-Grade/ 3 Q-Grade I-Grade/ 6 Q-Grade ...
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... T Q-Grade MCCH and High Time Table 50: CCLK Input Low and High Time Symbol T CCLK Low and High time SCCL, T SCCH DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet ConfigRate Temperature Setting Range 1 I-Grade/ (power-on value) Q-Grade I-Grade/ ...
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... Notes: 1. The numbers in this table are based on the operating conditions set forth in 2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet T T DCC ...
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... CCPAR at the CCLK input pin Notes: 1. The numbers in this table are based on the operating conditions set forth in 2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet T SMCSCC T SMCCW ...
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... DCC T Hold time on DIN data input after CCLK rising edge CCD DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point these pins become user-I/O pins ...
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... These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The post- configuration timing can be different to support the specific needs of the application loaded into the FPGA. 2. Subtract additional printed circuit board routing delay as required by the application. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description www ...
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... DCC T Hold time on D[7:0] data inputs after CCLK rising edge CCD DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Mode input pins M[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point the mode pins become user-I/O pins ...
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... The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s PUDC_B pin is High or Low. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Requirement ≤ ...
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... The numbers in this table are based on the operating conditions set forth in 2. For details on JTAG, see “JTAG Configuration Mode and Boundary-Scan” in Chapter 9 of UG332, Spartan-3 Generation Configuration User Guide. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet T ...
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... THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Description of Revisions " ...