DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 49

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Serial Peripheral Interface Configuration Timing
X-Ref Target - Figure 13
Table 53: Timing for Serial Peripheral Interface Configuration Mode
DS705 (v1.1) January 20, 2009
Product Specification
(Open-Drain)
T
T
T
T
T
T
T
PROG_B
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
PUDC_B
Symbol
VS[2:0]
CSO_B
INIT_B
M[2:0]
CCLK
(Input)
(Input)
(Input)
(Input)
(Input)
MOSI
DIN
Shaded values indicate specifications on attached SPI Flash PROM.
R
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
MOSI output valid delay after CCLK falling edge
Setup time on DIN data input before CCLK rising edge
Hold time on DIN data input after CCLK rising edge
T
MINIT
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
Figure 13: Waveforms for Serial Peripheral Interface Configuration
<1:1:1>
<0:0:1>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
T
CCLK1
Description
T
CSS
Command
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
(msb)
T
CCO
www.xilinx.com
T
DSU
T
MCCL1
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Command
(msb-1)
T
MCCH1
T
DH
Minimum
Data
50
0
0
T
T
New ConfigRate active
CCLK1
See
See
See
See
MCCL n
Data
T
T
V
Maximum
DCC
Table 47
Table 47
Table 51
Table 51
-
-
-
Data
DS705_14_061908
T
T
CCLK n
T
CCD
MCCH n
Units
Data
ns
ns
ns
49