Manufacturer Part NumberHW-V5-ML506-UNI-G
ManufacturerXilinx Inc
SeriesVirtex™-5 SXT
HW-V5-ML506-UNI-G datasheet

Specifications of HW-V5-ML506-UNI-G

ContentsEvaluation Platform, DVI Adapter and CompactFlash CardSilicon ManufacturerXilinx
FeaturesJTAG Programming Interface, Platform Flash, External ClockingKit ContentsBoard, Cable, PSU, CD, Docs
Silicon Family NameVirtex-5Silicon Core NumberXC5VSX50TFFG1136
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With/related ProductsXC5VSX50TFFG1136  
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L507 Evaluation
Evaluation Platform
User Guide [optional]
User Guide
UG347 (v3.1.1) October 7, 2009 [optional]
UG347 (v3.1.1) October 7, 2009

HW-V5-ML506-UNI-G Summary of contents

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    ML505/ML506/M ML505/ML506/ML507 L507 Evaluation Evaluation Platform Platform User Guide [optional] User Guide UG347 (v3.1.1) October 7, 2009 [optional] UG347 (v3.1.1) October 7, 2009 R ...

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    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...

  • Page 3

    Date Version Updated document to include ML507 board. 05/19/08 3.0 Added notes for Updated Updated link in 07/21/08 3.0.1 Updated Added content to 11/10/08 3.1 “Configuration Options,” page PROM throughout. 10/07/09 3.1.1 Minor typographical edit. UG347 (v3.1.1) October 7, 2009 ...

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    ML505/ML506/ML507 Evaluation Platform www.xilinx.com UG347 (v3.1.1) October 7, 2009 ...

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    Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    JTAG Configuration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    R About This Guide The ML50x evaluation platforms enable designers to investigate and experiment with features of Virtex®-5 FPGAs. This user guide describes the features and operation of the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms. Guide Contents ...

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    Preface: About This Guide • Virtex-5 FPGA RocketIO GTP/GTX Transceiver User Guide This guide describes the RocketIO™ GTP/GTX transceivers available in the Virtex-5 LXT and SXT platform devices. • Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller User Guide This user ...

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    R Online Document The following conventions are used in this document: Convention Blue text Red text Blue, underlined text ML505/ML506/ML507 Evaluation Platform UG347 (v3.1.1) October 7, 2009 Typographical Conventions Meaning or Use Cross-reference link to a See the section location ...

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    Preface: About This Guide 10 www.xilinx.com ML505/ML506/ML507 Evaluation Platform UG347 (v3.1.1) October 7, 2009 R ...

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    R ML505/ML506/ML507 Evaluation Platform Overview ML505, ML506, and ML507 Evaluation Platforms (referred to as ML50x in this guide) enable designers to investigate and experiment with features of the Virtex-5 LXT, SXT, and FXT FPGAs. This user guide describes the features ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform • RS-232 serial port, DB9 and header for second serial port • 16-character x 2-line LCD display • One 8-Kb IIC EEPROM and other IIC capable devices • PS/2 mouse and keyboard connectors • Video ...

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    R Package Contents • Xilinx Virtex-5 FPGA ML50x Evaluation Platform • System ACE CompactFlash card • Power supply • DVI to VGA adaptor Additional Information Additional information and support material is located at: • ML505 - • ML506 - • ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Block Diagram Figure 1-1 shows a block diagram of the ML50x Evaluation Platform (board). CPLD Misc. Glue Logic 16 Flash GPIO (Button/LED/DIP Switch) Piezo/Speaker PLL Clock Generator Plus User Oscillator System Monitor SMA (Differential In/Out ...

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    R Detailed Description The ML505 Evaluation Platform is shown in (back). The numbered sections on the pages following the figures contain details on each feature Keybd 16 Mouse 22 Figure 1-2: Detailed Description of Virtex-5 ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Figure 1-3: Detailed Description of Virtex-5 FPGA ML505 Components (Back) Note: The label on the CompactFlash (CF) card shipped with your board might differ from the one shown www.xilinx.com ML505/ML506/ML507 ...

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    R 1. Virtex-5 FPGA A Xilinx Virtex-5 FPGA is installed on the board. See device details. Configuration The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master SelectMAP, Slave SelectMAP, Byte-wide Peripheral Interface (BPI) Up, BPI Down, ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Digitally Controlled Impedance Some FPGA banks can support the digitally controlled impedance (DCI) feature in Virtex-5 FPGAs. Support for DCI is summarized in Table 1-2: DCI Capability of FPGA Bank FPGA Bank ...

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    R DDR2 Memory Expansion The DDR2 interface support user installation of SODIMM modules with more memory since higher order address and chip select signals are also routed from the SODIMM to the FPGA. DDR2 Clock Signal Two matched length pairs ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform FPGA. The programmable clock generator provides the following factory default single- ended outputs: • 25 MHz to the Ethernet PHY (U16) • 14 MHz to the audio codec (U22) • 27 MHz to the USB ...

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    R 7. User and Error LEDs (Active-High) There are a total of 15 active-High LEDs directly controllable by the FPGA: • Eight green LEDs are general purpose LEDs arranged in a row • Five green LEDs are positioned next to ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform 8. User Pushbuttons (Active-High) Five active-High user pushbuttons are available for general purpose usage and are arranged in a North-East-South-West-Center orientation (only the center one is cited in Figure 1-2, page Table 1-7: User Pushbutton ...

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    R Table 1-9: Expansion I/O Differential Connections (J4) J4 Differential Pin Pair Pos Single-Ended Expansion I/O Connectors Header J6 contains 32 single-ended signal connections ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Table 1-10: Expansion I/O Single-Ended Connections (J6) (Cont’d) J6 Pin Other ...

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    R have the IIC pull-up resistors present on the expansion card. Bidirectional level shifting transistors allow the expansion card to utilize 2. signaling on the IIC bus. Power supply connections to the expansion connectors provide ground, 2.5V, 3.3V, ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Table 1-11: Additional Expansion I/O Connections (J5) (Cont’d) J5 Pin 11. Stereo AC97 Audio Codec The ML50x board has an AC97 audio codec (U22) to permit audio processing. ...

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    R 12. RS-232 Serial Port The ML50x board contains one male DB-9 RS-232 serial port, allowing the FPGA to communicate serial data with another device. The serial port is wired as a host (DCE) device. Therefore, a null modem cable ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform The DVI connector monitor’s configuration parameters. These parameters can be read by the FPGA using the VGA IIC bus. Table 1-14: DVI Controller Connections Net Name DVI_D[0] DVI_D[1] DVI_D[2] DVI_D[3] DVI_D[4] DVI_D[5] DVI_D[6] DVI_D[7] DVI_D[8] ...

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    R The CompactFlash card shipped with the board is correctly formatted to enable the System ACE CF controller to access the data stored in the card. The System ACE CF controller requires a FAT16 file system, with only one reserved ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Caution! Improper insertion can cause a short with the traces or components on the board. The System ACE MPU port is connected to the FPGA. This connection allows the FPGA to use the System ACE ...

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    ... UG347 (v3.1.1) October 7, 2009 Table 1-15. Bit[2] Definition and Value Definition and Value PHYADR[ PHYADR[ ENA_PAUSE = 0 PHYADR[ ANEG[ ANEG[ ANEG[ ENA_XC = 1 HWCFG_MODE[ HWCFG_MODE[ (Set by J23 and J24) DIS_FC = 1 DIS_SLEEP = 1 SEL_BDT = 0 INT_POL = 1 www.xilinx.com Detailed Description Bit[1] Bit[0] Definition and Value PHYADR[ PHYADR[ ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Jumpers J22, J23, and J24 allow the user to select the default interface that the PHY uses (Figure 1-4 GMII/MII to copper J22 J23 J24 J56 Note: J56 = SATA Clock Select Table 1-16: PHY ...

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    R The Platform Flash PROM can program the FPGA by using the master or slave configuration in serial or parallel (SelectMap) modes. The Platform Flash PROM is programmed using Xilinx iMPACT software through the board’s JTAG chain. See the “Configuration ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform 5V Brick 6A J15 SW1 Off On 26. AC Adapter and Input Power Switch/Jack The board can be powered by one of two 5V sources; P20 5.5 mm barrel type plug ...

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    R 28. DONE LED The DONE LED indicates the status of the DONE pin on the FPGA. It should be lighted when the FPGA is successfully configured. 29. INIT LED The INIT LED lights upon power-up to indicate that the ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Configuration Address [2:0] allows the user to select among multiple configuration images. For System ACE configuration eight possible configurations can be stored card. The Platform Flash PROM and Linear Flash ...

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    R 34. IIC Fan Controller and Temperature/Voltage Monitor Onboard temperature and voltage monitoring and control is handled by an Analog Devices ADT7476A chip. This chip is controlled via IIC and can provide the following functions: • Measure the voltage of ...

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    R The JTAG debug port supports the four required JTAG signals: TCK, TMS, TDI, and TDO. It also implements the optional TRST signal. The frequency of the JTAG clock signal can range from 0 MHz (DC) to one-half of the ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform Table 1-21: CPU Trace/Debug Connection to FPGA (Cont’d) Pin Name - - CPU_TDO TRC_VSENSE - - CPU_TCK MICTOR_16 CPU_TMS MICTOR_18 FPGA_CS0_B (CPU_TDI) MICTOR_20 CPU_TRST MICTOR_22 MICTOR_23 TRC_TS1O MICTOR_25 TRC_TS2O MICTOR_27 TRC_TS1E MICTOR_29 TRC_TS2E MICTOR_31 TRC_TS3 ...

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    R CPU JTAG Header Pinout Figure 1-8 shows J12, the 16-pin header that can be used to debug the software operating in the CPU with debug tools such as Parallel Cable IV or third party tools. CPU JTAG Connection to ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform 38. Rotary Encoder The board provides connectivity to a rotary encoder (Panasonic EVQWK4001) with 15 detents, pushbutton, and two phase output signals for direction of rotation interpretation. One complete revolution of the rotary wheel produces ...

  • Page 43

    R 40. PCI Express Interface Table 1-25 RocketIO transceivers to the Virtex-5 FPGA integrated Endpoint block for PCIe designs. See the Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs more information. Table 1-25: PCIe Connection to FPGA ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform 41. Serial-ATA Host Connectors Serial-ATA (SATA) is the next generation of the ATA interface used for storage devices such as hard disks. The board contains two SATA host connectors that can be connected to a ...

  • Page 45

    R Table 1-27: Configuration for SFP Module Control and Status Signals SFP Control/Status Signal SFP TX FAULT SFP TX DISABLE SFP MOD DETECT SFP RT SEL SFP LOS Table 1-28: SFP Module Connections SFP Signal CLKBUF_Q0_P CLKBUF_Q0_N SFP_RX_P SFP_RX_N SFP_TX_P ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform 43. GTP/GTX Clocking Circuitry Overview Low jitter LVDS clock sources on the board provide high-quality reference clocks for the GTP/GTX transceivers. Different clock sources are provided to support each of the transceiver interfaces on the ...

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    R Table 1-31: Configurations for Clock Source and Frequency Options DIP Switch SW6 [1:8] Value SEL1 SEL0 ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform 44. Soft Touch Landing Pad An Agilent Pro Series soft touch landing pad is available for use with a logic analyzer. The landing pad is designed for use with the Agilent E5404/06A 34-channel single-ended probe. ...

  • Page 49

    R Table 1-33: Landing Pad Signals on XGI Header (Cont’d) Pad Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 45. System ...

  • Page 50

    Chapter 1: ML505/ML506/ML507 Evaluation Platform made as the AUX channels are also used as general-purpose I/O on the XGI connectors (see “10. XGI Expansion Headers,” page 22 still available for use with the System Monitor functions, but they will not ...

  • Page 51

    R Table 1-34: System Monitor Connections (Cont’d) External Input VAUXN[5] VAUXP[5] VAUXN[6] VAUXP[6] VAUXN[7] VAUXP[7] VAUXN[8] VAUXP[8] VAUXN[9] VAUXP[9] VAUXN[10] VAUXP[10] VAUXN[11] VAUXP[11] VAUXN[12] VAUXP[12] VAUXN[13] VAUXP[13] VAUXN[14] VAUXP[14] VAUXN[15] VAUXP[15] ML505/ML506/ML507 Evaluation Platform UG347 (v3.1.1) October 7, 2009 FPGA ...

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    Chapter 1: ML505/ML506/ML507 Evaluation Platform IIC Buses The board supports four IIC buses; Main, Video, SFP, and DDR2. Each of the IIC buses has 1K pull-ups on its SCL and SDA signals. each of the four buses. Table 1-35: IIC ...

  • Page 53

    R Configuration Options The FPGA on the ML50x Evaluation Platform can be configured by the following major devices: • Xilinx download cable (JTAG) • System ACE controller (JTAG) • Two Platform Flash PROMs • Linear Flash memory • SPI Flash ...

  • Page 54

    Chapter 1: ML505/ML506/ML507 Evaluation Platform Pressing the System ACE reset button also causes the System ACE controller to program the FPGA if a CompactFlash card is present. Platform Flash PROM Configuration The Platform Flash PROMs can also be used to ...

  • Page 55

    R Board Revisions This appendix describes the major differences in the ML50x platforms Table A-1: ML50x Platform Details Platform Device XC5VLX50T-1C ML505 XC5VLX50T-1CES XC5VSX50T-1C ML506 XC5VSX50T-1CES ML507 XC5VFX70T-1CES Notes: 1. Where AVCC_PLL voltage is set to 1.2V. (R176 = 2.43K ...

  • Page 56

    ML505/ML506/ML507 Evaluation Platform UG347 (v3.1.1) October 7, 2009 R ...

  • Page 57

    R Programming the IDT Clock Chip Overview The ML50x evaluation boards feature an Integrated Device Technology (IDT) 3.3V EEPROM Programmable Clock Generator that is pre-programmed at the factory. In the event the chip programming is changed, the instructions in this ...

  • Page 58

    Figure B-2: Programming the IDT5V9885 on the ML50x Using iMPACT 7. To finish programming the chip, cycle the power by turning off the board power switch. 8. After turning the board back on, verify that the clock frequencies are correct. ...

  • Page 59

    R References Documents specific to the ML50x Evaluation Platform: 1. UG348 2. UG349, ML505/ML506/ML507 Reference Design User Guide. 3. Lab Resources: ML505, ML506, ML507. Documents supporting Virtex-5 FPGAs: 4. DS100, Virtex-5 FPGA Family Overview. 5. DS202, Virtex-5 FPGA Data Sheet: ...

  • Page 60

    The Xilinx ChipScope Pro Analyzer: 24. UG029, ChipScope Pro Software and Cores User Guide. 25. UG213, ChipScope Pro Serial I/O Toolkit User Guide. 60 ChipScope Pro Tool Web page offers the following material supporting the www.xilinx.com ML505/ML506/ML507 Evaluation Platform UG347 ...